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Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/.gitignore

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+/.qsys_edit
+/db
+/neorv32_test_qsys
+/*.sopcinfo
+/*.rpt
+/output_files
+/incremental_db
+/*.qws

Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/README.md

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+# NEORV32 Test Setup using the NEORV32 as a Nios II drop-in replacement
+
+This setup provides a very simple "demo setup" that uses the NEORV32 Qsys/Platform Designer component
+so that the NEORV32 can be used as a drop-in replacement of the Nios II soft CPU from Intel.
+The demo is running on the Terasic DE0-Nano FPGA Board.
+
+The design is based on the de0-nano-test-setup, but the NEORV32 cpu is added as a QSys/Platform Designer
+component. As an example the DMEM is "external" and uses an Platform Designer SRAM block.
+
+![NEORV32 in Platform Designer](figures/neorv32_platform_designer.png)
+
+For details about the design and use of the NEORV32 as a Qsys/Platform Designer component please
+look at the Qsys component files and documentation here [`NEORV32 Qsys Component`](../neorv32_qsys_component)
+
+It uses the simplified simple example top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
+
+* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593)
+* FPGA: Intel Cyclone-IV `EP4CE22F17C6N`
+* Toolchain: Intel Quartus Prime (tested with Quartus Prime 18.1.1 - Lite Edition)
+
+
+### NEORV32 Configuration
+
+For NEORV32 configuration the default values of the neorv32_top in version 1.6.0 are used
+with a few exceptions:
+
+* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (external DMEM), No bootloader
+* Tested with version [`1.6.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
+* Clock: 50MHz from on-board oscillator
+* Reset: via on-board button "KEY0"
+* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0")
+* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header
+  * `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4")
+  * `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6")
+
+### FPGA Utilization
+
+```
+Total logic elements 4,064 / 22,320 ( 18 % )
+Total registers      1932
+Total pins           12 / 154 ( 8 % )
+Total virtual pins   0
+Total memory bits    230,400 / 608,256 ( 38 % )
+Embedded Multiplier  9-bit elements	0 / 132 ( 0 % )
+Total PLLs           0 / 4 ( 0 % )
+```
+
+
+## How To Run
+
+Open the Quartus project file, compile and upload to FPGA.

Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/User_Components.ipx

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+<library>
+	<path path="../neorv32_qsys_component/**/*" />
+</library>

Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.qpf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+# Date created = 21:29:54  June 08, 2021
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.1"
+DATE = "21:29:54  June 08, 2021"
+
+# Revisions
+
+PROJECT_REVISION = "de0-nano-test-setup"

Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.qsf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+# Date created = 21:29:54  June 08, 2021
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		de0-nano-test-setup_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE22F17C6
+set_global_assignment -name TOP_LEVEL_ENTITY neorv32_ProcessorTop_Test
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53  APRIL 10, 2021"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id neorv32_ProcessorTop_Test
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id neorv32_ProcessorTop_Test
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id neorv32_ProcessorTop_Test
+set_location_assignment PIN_R8 -to clk_i
+set_location_assignment PIN_J15 -to rstn_i
+set_location_assignment PIN_C3 -to uart0_txd_o
+set_location_assignment PIN_A3 -to uart0_rxd_i
+set_location_assignment PIN_L3 -to gpio_o[7]
+set_location_assignment PIN_B1 -to gpio_o[6]
+set_location_assignment PIN_F3 -to gpio_o[5]
+set_location_assignment PIN_D1 -to gpio_o[4]
+set_location_assignment PIN_A11 -to gpio_o[3]
+set_location_assignment PIN_B13 -to gpio_o[2]
+set_location_assignment PIN_A13 -to gpio_o[1]
+set_location_assignment PIN_A15 -to gpio_o[0]
+set_global_assignment -name QSYS_FILE neorv32_test_qsys.qsys
+set_global_assignment -name QIP_FILE ../neorv32_qsys_component/neorv32_qsys.qip
+set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_application_image.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_bootloader_image.vhd
+set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_dmem.entity.vhd -library neorv32
+set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_imem.entity.vhd -library neorv32
+set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_dmem.default.vhd -library neorv32
+set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_imem.default.vhd -library neorv32
+set_global_assignment -name VHDL_FILE neorv32_ProcessorTop_Test.vhd
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id neorv32_ProcessorTop_Test

Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.sdc

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+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
+create_clock -name {clk_i} -period 20.0 -waveform { 0.0 10.0 } [get_ports {clk_i}]

Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/neorv32_ProcessorTop_Test.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library work;
+
+entity neorv32_ProcessorTop_Test is port (
+    clk_i                   : in std_logic;
+    rstn_i                  : in std_logic;
+    gpio_o                  : out std_logic_vector(7 downto 0);
+    uart0_txd_o             : out std_logic;
+    uart0_rxd_i             : in std_logic);
+end neorv32_ProcessorTop_Test;
+
+----------------------------------------------------------------------------------------------------
+architecture rtl of neorv32_ProcessorTop_Test is
+----------------------------------------------------------------------------------------------------
+
+component neorv32_test_qsys is
+port (
+    clk_clk                 : in std_logic;
+    perf_uart0_uart0_txd_o  : out std_logic;
+    perf_uart0_uart0_rxd_i  : in std_logic;
+    perf_gpio_gpio_o        : out std_logic_vector(31 downto 0);
+    perf_gpio_gpio_i        : in std_logic_vector(31 downto 0);
+    reset_reset_n           : in std_logic);
+end component;
+
+signal  perf_gpio_gpio_o    : std_logic_vector(31 downto 0);
+
+begin
+
+    gpio_o <= perf_gpio_gpio_o(7 downto 0);
+
+    my_riscv_core : neorv32_test_qsys
+    port map (
+        clk_clk => clk_i,
+        perf_gpio_gpio_o => perf_gpio_gpio_o,
+        perf_gpio_gpio_i => (others => '0'),
+        perf_uart0_uart0_txd_o => uart0_txd_o,
+        perf_uart0_uart0_rxd_i => uart0_rxd_i,
+        reset_reset_n => rstn_i);
+
+end rtl;