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# NEORV32 Test Setup for the Terasic Cyclone-V GX Starter Kit FPGA Board
This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Terasic Cyclone-V GX Starter Kit board.
It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor
top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
* FPGA Board: :books: [Terasic Cyclone-V GX Starter Kit FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830)
* FPGA: Intel Cyclone-V GX `5CGXFC5C6F27C7N`
* Toolchain: Intel Quartus Prime (tested with Quartus Prime 20.1.0 - Lite Edition)
### NEORV32 Configuration
:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for
configuration and entity details and `create_project.tcl` for the according FPGA pin mapping.
* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors, 40-bit wide)
* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM
* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT`
* Tested with version [`1.5.9.4`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
* Clock: 50MHz from on-board oscillator
* Reset: via on-board button "KEY0"
* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0")
* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board provided USB to UART converter
:warning: The default [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity
is configured for a 100MHz input clock. Since the on-board clock generator of the Cyclone-V GX Starter Kit board needs I2C to be programmed, the fixed 50MHz clock on bank 5B, pin R20 is used for this test setup, and the test setup has to be modified accordingly.
This is automatically done by the `create_project.tcl` TCL script, which makes a local copy of the original test setup VHDL file
(in *this* folder) and uses `sed` to configure the `CLOCK_FREQUENCY` generic (in the local copy) for 50MHz. The local copy is then used as actual
top entity.
### FPGA Utilization
```
Logic utilization (in ALMs) 1,442 / 29,080 ( 5 % )
Total registers 1771
Total pins 12 / 364 ( 3 % )
Total virtual pins 0
Total block memory bits 231,424 / 4,567,040 ( 5 % )
Total DSP Blocks 0 / 150 ( 0 % )
Total HSSI RX PCSs 0 / 6 ( 0 % )
Total HSSI PMA RX Deserializers 0 / 6 ( 0 % )
Total HSSI TX PCSs 0 / 6 ( 0 % )
Total HSSI PMA TX Serializers 0 / 6 ( 0 % )
Total PLLs 0 / 12 ( 0 % )
Total DLLs 0 / 4 ( 0 % )
```
## How To Run
The `create_project.tcl` TCL script in this directory can be used to create a complete Quartus project.
If not already available, this script will create a `work` folder in this directory.
1. start Quartus (in GUI mode)
2. in the menu line click "View/Utility Windows/Tcl console" to open the Tcl console
3. use the console to navigate to **this** folder: `cd .../setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup`
4. execute `source create_project.tcl` - this will create and open the actual Quartus project in this folder. Do NOT run the Quartus-supplied tcl setup script, as that will change all assignment names.
5. if a "select family" prompt appears, go to the "Board" tab, select the "Cyclone V GX Starter Kit" board and click OK
6. double click on "Compile Design" in the "Tasks" window. This will synthesize, map and place & route your design and will also generate the actual FPGA bitstream
7. when the process is done open the programmer (for example via "Tools/Programmer") and click "Start" in the programmer window to upload the bitstream to your FPGA
8. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration:
19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline)
9. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example)
and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources.

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# make a local copy of original "./../../rtl/test_setups/neorv32_test_setup_bootloader.vhd " file
# and modify the default clock frequency: set to 50MHz
set shell_script "cp -f ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd . && sed -i 's/100000000/50000000/g' neorv32_test_setup_bootloader.vhd "
exec sh -c $shell_script
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
# Quartus Prime: Generate Tcl File for Project
# File: terasic-cyclone-V-gx=starter-kit_test.tcl
# Generated on: Sat Apr 10 16:57:48 2021
# Load Quartus Prime Tcl Project package
package require ::quartus::project
set need_to_close_project 0
set make_assignments 1
# Check that the right project is open
if {[is_project_open]} {
if {[string compare $quartus(project) "terasic-cyclone-V-gx-starter-kit-test-setup"]} {
puts "Project terasic-cyclone-V-gx-starter-kit-test-setup is not open"
set make_assignments 0
}
} else {
# Only open if not already open
if {[project_exists de0-nano-test-setup]} {
project_open -revision terasic-cyclone-V-gx-starter-kit-setup terasic-cyclone-V-gx-starter-kit-test-setup
} else {
project_new -revision terasic-cyclone-V-gx-starter-kit-test-setup terasic-cyclone-V-gx-starter-kit-test-setup
}
set need_to_close_project 1
}
# Make assignments
if {$make_assignments} {
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_bootloader
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "TUE JUN 4 20:41:15 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "Cyclone V GX Starter Kit"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
# core VHDL files
set core_src_dir [glob ./../../../rtl/core/*.vhd]
foreach core_src_file $core_src_dir {
set_global_assignment -name VHDL_FILE $core_src_file -library neorv32
}
# top entity: use local modified copy of the original test setup
set_global_assignment -name VHDL_FILE "neorv32_test_setup_bootloader.vhd"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i
set_instance_assignment -name IO_STANDARD "1.2 V" -to rstn_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to uart0_rxd_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to uart0_txd_o
set_location_assignment PIN_R20 -to clk_i
set_location_assignment PIN_P11 -to rstn_i
set_location_assignment PIN_L7 -to gpio_o[0]
set_location_assignment PIN_K6 -to gpio_o[1]
set_location_assignment PIN_D8 -to gpio_o[2]
set_location_assignment PIN_E9 -to gpio_o[3]
set_location_assignment PIN_A5 -to gpio_o[4]
set_location_assignment PIN_B6 -to gpio_o[5]
set_location_assignment PIN_H8 -to gpio_o[6]
set_location_assignment PIN_H9 -to gpio_o[7]
set_location_assignment PIN_M9 -to uart0_rxd_i
set_location_assignment PIN_L9 -to uart0_txd_o
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# Commit assignments
export_assignments
}