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Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/.gitignore vendored Normal file
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/*
!.gitignore
!README.md
!system_pll/
system_pll/*
!system_pll/system_pll.ipx
!system_pll/rtl/
system_pll/rtl/*
!system_pll/rtl/system_pll.v
!source/
source/*
!source/impl_1.xcf
!*.vhd
!*.rdf
!*.pdc
!*.bin

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# NEORV32 Example Setup for the tinyVision.ai Inc. "UPduino v3.0" FPGA Board
This example setup turns the UPduino v3.0 board, which features a Lattice iCE40 UltraPlus FPGA, into a medium-scale NEORV32 *microcontroller*.
The processor setup provides 64kB of data and instruction memory, an RTOS-capable CPU (privileged architecture)
and a set of standard peripherals like UART, TWI and SPI.
* FPGA Board: :books: [tinyVision.ai Inc. UPduino v3 FPGA Board (GitHub)](https://github.com/tinyvision-ai-inc/UPduino-v3.0/),
:credit_card: buy on [Tindie](https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/)
* FPGA: Lattice iCE40 UltraPlus 5k `iCE40UP5K-SG48I`
* Toolchain: Lattice Radiant (tested with Radiant version 3.0.0), using *Lattice Synthesis Engine (LSE)*
* Top entity: [`neorv32_upduino_v3_top.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_upduino_v3_top.vhd) (instantiates NEORV32 top entity)
### Processor Configuration
- [x] CPU: `rv32imacu_Zicsr_Zicntr` (reduced CPU `[m]instret` & `[m]cycle` counter width!)
- [x] Memory: 64 kB instruction memory (internal IMEM), 64 kB data memory (internal DMEM), 4 kB bootloader ROM
- [x] Peripherals: `GPIO`, `MTIME`, `UART0`, `SPI`, `TWI`, `PWM`, `WDT`, `TRNG`
- [x] Clock: 24 MHz from on-chip HF oscillator (via PLL)
- [x] Reset: via PLL "locked" signal; external "reset" via FPGA re-reconfiguration pin (`creset_n`)
- [x] Tested with processor version [`1.6.1.6`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
- [x] On-board FPGA bitstream flash storage can also be used to store/load NEORV32 application software (via the bootloader)
:information_source: This setup uses optimized platform-specific memory modules for the internal data and instruction memories (DMEM & IMEM). Each memory uses two
UltraPlus SPRAM primitives (total memory size per memory = 2 x 32kB = 64kB). VHDL source file for platform-specific IMEM:
[`neorv32_imem.ice40up_spram.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_imem.ice40up_spram.vhd);
VHDL source file for platform-specific DMEM: [`neorv32_dmem.ice40up_spram.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_dmem.ice40up_spram.vhd).
These platform-specific memories are used *instead* of the default platform-agnostic modules from the core's `rtl/core/mem` folder.
### Interface Signals
:information_source: See [`neorv32_upduino_v3.pdc`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_upduino_v3.pdc)
for the FPGA pin mapping.
| Top Entity Signal | FPGA Pin | Package Pin | Board Header Pin |
|:------------------------------|:----------:|:------------:|:-----------------|
| `flash_csn_o` (spi_cs[0]) | IOB_35B | 16 | J3-1 |
| `flash_sck_o` | IOB_34A | 15 | J3-2 |
| `flash_sdo_o` | IOB_32A | 14 | J3-3 |
| `flash_sdi_i` | IOB_33B | 17 | J3-4 |
| `gpio_i(0)` | IOB_3B_G6 | 44 | J3-9 |
| `gpio_i(1)` | IOB_8A | 4 | J3-10 |
| `gpio_i(2)` | IOB_9B | 3 | J3-11 |
| `gpio_i(3)` | IOB_4A | 48 | J3-12 |
| `gpio_o(0)` (status LED) | IOB_5B | 45 | J3-13 |
| `gpio_o(1)` | IOB_2A | 47 | J3-14 |
| `gpio_o(2)` | IOB_0A | 46 | J3-15 |
| `gpio_o(3)` | IOB_6A | 2 | J3-16 |
| - | - | - | - |
| **reconfigure FPGA** ("_reset_") | CRESET | 8 | J2-3 |
| `pwm_o(0)` | `gpio_i(0)` (red)| RGB2 | 41 | J2-5 |
| `pwm_o(1)` (green) | RGB0 | 39 | J2-6 |
| `pwm_o(2)` (blue) | RGB1 | 40 | J2-7 |
| `twi_sda_io` | IOT_42B | 31 | J2-9 |
| `twi_scl_io` | IOT_45A_G1 | 37 | J2-10 |
| `spi_sdo_o` | IOT_44B | 34 | J2-11 |
| `spi_sck_o` | IOT_49A | 43 | J2-12 |
| `spi_csn_o` (spi_cs[1]) | IOT_48B | 36 | J2-13 |
| `spi_sdi_i` | IOT_51A | 42 | J2-14 |
| `uart_txd_o` (UART0) | IOT_50B | 38 | J2-15 |
| `uart_rxd_i` (UART0) | IOT_41A | 28 | J2-16 |
:information_source: The TWI signals (`twi_sda_io` and `twi_scl_io`) and the reset input (`rstn_i`) require an external pull-up resistor.
GPIO output 0 (`gpio_o(0)`, also connected to the RGB drive) is used as output for a high-active **status LED** driven by the bootloader.
### FPGA Utilization
```
Number of slice registers: 1754 out of 5280 (33%)
Number of I/O registers: 11 out of 117 (9%)
Number of LUT4s: 4882 out of 5280 (92%)
Number of DSPs: 0 out of 8 (0%)
Number of I2Cs: 0 out of 2 (0%)
Number of High Speed OSCs: 1 out of 1 (100%)
Number of Low Speed OSCs: 0 out of 1 (0%)
Number of RGB PWM: 0 out of 1 (0%)
Number of RGB Drivers: 1 out of 1 (100%)
Number of SCL FILTERs: 0 out of 2 (0%)
Number of SRAMs: 4 out of 4 (100%)
Number of WARMBOOTs: 0 out of 1 (0%)
Number of SPIs: 0 out of 2 (0%)
Number of EBRs: 15 out of 30 (50%)
Number of PLLs: 1 out of 1 (100%)
```
### FPGA Setup
1. start Lattice Radiant (in GUI mode)
2. click on "open project" and select `neorv32_upduino_v3.rdf` from this folder
3. click the :arrow_forward: button to synthesize, map, place and route the design and to generate a programming file
4. when done open the programmer (for example via "Tools" -> "Programmer"); you will need a programmer configuration, which will be created in the next steps; alternatively,
you can use the pre-build configuration `source/impl_1.xcf`
5. in the programmer double click on the field under "Operation" (_fast configuration_ should be the default) and select "External SPI Memory" as "Target Memory"
6. select "SPI Serial Flash" under "SPI Flash Options / Family"
7. select "WinBond" under "SPI Flash Options / Vendor"
8. select "W25Q32" under "SPI Flash Options / Device"
9. close the dialog by clicking "ok"
10. click on "Program Device"

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-- #################################################################################################
-- # << NEORV32 - Processor-Internal DMEM for Lattice iCE40 UltraPlus >> #
-- # ********************************************************************************************* #
-- # Memory has a physical size of 64kb (2 x SPRAMs). #
-- # Logical size DMEM_SIZE must be less or equal. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
library iCE40UP;
use iCE40UP.components.all; -- for device primitives
architecture neorv32_dmem_rtl of neorv32_dmem is
-- advanced configuration --------------------------------------------------------------------------------
constant spram_sleep_mode_en_c : boolean := false; -- put DMEM into sleep mode when idle (for low power)
-- -------------------------------------------------------------------------------------------------------
-- IO space: module base address --
constant hi_abb_c : natural := 31; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit
-- local signals --
signal acc_en : std_ulogic;
signal mem_cs : std_ulogic;
signal rdata : std_ulogic_vector(31 downto 0);
signal rden : std_ulogic;
-- SPRAM signals --
signal spram_clk : std_logic;
signal spram_addr : std_logic_vector(13 downto 0);
signal spram_di_lo : std_logic_vector(15 downto 0);
signal spram_di_hi : std_logic_vector(15 downto 0);
signal spram_do_lo : std_logic_vector(15 downto 0);
signal spram_do_hi : std_logic_vector(15 downto 0);
signal spram_be_lo : std_logic_vector(03 downto 0);
signal spram_be_hi : std_logic_vector(03 downto 0);
signal spram_we : std_logic;
signal spram_pwr_n : std_logic;
signal spram_cs : std_logic;
begin
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based DMEM." severity note;
assert not (DMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: DMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error;
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
mem_cs <= acc_en and (rden_i or wren_i);
-- Memory Access --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
dmem_spram_lo_inst : SP256K
port map (
AD => spram_addr, -- I
DI => spram_di_lo, -- I
MASKWE => spram_be_lo, -- I
WE => spram_we, -- I
CS => spram_cs, -- I
CK => spram_clk, -- I
STDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
PWROFF_N => '1', -- I
DO => spram_do_lo -- O
);
dmem_spram_hi_inst : SP256K
port map (
AD => spram_addr, -- I
DI => spram_di_hi, -- I
MASKWE => spram_be_hi, -- I
WE => spram_we, -- I
CS => spram_cs, -- I
CK => spram_clk, -- I
STDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
PWROFF_N => '1', -- I
DO => spram_do_hi -- O
);
-- access logic and signal type conversion --
spram_clk <= std_logic(clk_i);
spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2));
spram_di_lo <= std_logic_vector(data_i(15 downto 00));
spram_di_hi <= std_logic_vector(data_i(31 downto 16));
spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable
spram_cs <= std_logic(mem_cs);
spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable
spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable
spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected
rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo);
buffer_ff: process(clk_i)
begin
if rising_edge(clk_i) then
ack_o <= mem_cs;
rden <= acc_en and rden_i;
end if;
end process buffer_ff;
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
end neorv32_dmem_rtl;

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-- #################################################################################################
-- # << NEORV32 - Processor-Internal IMEM for Lattice iCE40 UltraPlus >> #
-- # ********************************************************************************************* #
-- # Memory has a physical size of 64kb (2 x SPRAMs). #
-- # Logical size IMEM_SIZE must be less or equal. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
library iCE40UP;
use iCE40UP.components.all; -- for device primitives
architecture neorv32_imem_rtl of neorv32_imem is
-- advanced configuration --------------------------------------------------------------------------------
constant spram_sleep_mode_en_c : boolean := false; -- put IMEM into sleep mode when idle (for low power)
-- -------------------------------------------------------------------------------------------------------
-- IO space: module base address --
constant hi_abb_c : natural := 31; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit
-- local signals --
signal acc_en : std_ulogic;
signal mem_cs : std_ulogic;
signal rdata : std_ulogic_vector(31 downto 0);
signal rden : std_ulogic;
-- SPRAM signals --
signal spram_clk : std_logic;
signal spram_addr : std_logic_vector(13 downto 0);
signal spram_di_lo : std_logic_vector(15 downto 0);
signal spram_di_hi : std_logic_vector(15 downto 0);
signal spram_do_lo : std_logic_vector(15 downto 0);
signal spram_do_hi : std_logic_vector(15 downto 0);
signal spram_be_lo : std_logic_vector(03 downto 0);
signal spram_be_hi : std_logic_vector(03 downto 0);
signal spram_we : std_logic;
signal spram_pwr_n : std_logic;
signal spram_cs : std_logic;
begin
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based IMEM." severity note;
assert not (IMEM_AS_IROM = true) report "NEORV32 PROCESSOR CONFIG ERROR: ICE40 Ultra Plus SPRAM cannot be initialized by bitstream!" severity failure;
assert not (IMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: IMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error;
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
mem_cs <= acc_en and (rden_i or wren_i);
-- Memory Access --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
imem_spram_lo_inst : SP256K
port map (
AD => spram_addr, -- I
DI => spram_di_lo, -- I
MASKWE => spram_be_lo, -- I
WE => spram_we, -- I
CS => spram_cs, -- I
CK => spram_clk, -- I
STDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
PWROFF_N => '1', -- I
DO => spram_do_lo -- O
);
imem_spram_hi_inst : SP256K
port map (
AD => spram_addr, -- I
DI => spram_di_hi, -- I
MASKWE => spram_be_hi, -- I
WE => spram_we, -- I
CS => spram_cs, -- I
CK => spram_clk, -- I
STDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
PWROFF_N => '1', -- I
DO => spram_do_hi -- O
);
-- access logic and signal type conversion --
spram_clk <= std_logic(clk_i);
spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2));
spram_di_lo <= std_logic_vector(data_i(15 downto 00));
spram_di_hi <= std_logic_vector(data_i(31 downto 16));
spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable
spram_cs <= std_logic(mem_cs);
spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable
spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable
spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected
rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo);
buffer_ff: process(clk_i)
begin
if rising_edge(clk_i) then
ack_o <= mem_cs;
rden <= acc_en and rden_i;
end if;
end process buffer_ff;
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
end neorv32_imem_rtl;

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# Radiant pin mapping for the "tinyvision.ai Inc. UPduino v3" FPGA board
## Clock (on-chip hf oscillator)
#create_clock -period 41.666666 -name hf_osc_clk [get_nets hf_osc_clk]
## UART (uart0)
ldc_set_location -site {38} [get_ports uart_txd_o]
ldc_set_location -site {28} [get_ports uart_rxd_i]
## SPI - on-board flash
ldc_set_location -site {14} [get_ports flash_sdo_o]
ldc_set_location -site {15} [get_ports flash_sck_o]
ldc_set_location -site {16} [get_ports flash_csn_o]
ldc_set_location -site {17} [get_ports flash_sdi_i]
## SPI - user port
ldc_set_location -site {34} [get_ports spi_sdo_o]
ldc_set_location -site {43} [get_ports spi_sck_o]
ldc_set_location -site {36} [get_ports spi_csn_o]
ldc_set_location -site {42} [get_ports spi_sdi_i]
## TWI
ldc_set_location -site {31} [get_ports twi_sda_io]
ldc_set_location -site {37} [get_ports twi_scl_io]
## GPIO - input
ldc_set_location -site {44} [get_ports {gpio_i[0]}]
ldc_set_location -site {4} [get_ports {gpio_i[1]}]
ldc_set_location -site {3} [get_ports {gpio_i[2]}]
ldc_set_location -site {48} [get_ports {gpio_i[3]}]
## GPIO - output
ldc_set_location -site {45} [get_ports {gpio_o[0]}]
ldc_set_location -site {47} [get_ports {gpio_o[1]}]
ldc_set_location -site {46} [get_ports {gpio_o[2]}]
ldc_set_location -site {2} [get_ports {gpio_o[3]}]
## RGB power LED
ldc_set_location -site {39} [get_ports {pwm_o[0]}]
ldc_set_location -site {40} [get_ports {pwm_o[1]}]
ldc_set_location -site {41} [get_ports {pwm_o[2]}]

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<?xml version="1.0" encoding="UTF-8"?>
<RadiantProject version="4.2" title="neorv32_upduino_v3" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" default_implementation="impl_1">
<Options/>
<Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="lse" default_strategy="Strategy1">
<Options def_top="neorv32_upduino_v3_top" top="neorv32_upduino_v3_top"/>
<Source name="../../../rtl/core/neorv32_application_image.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_boot_rom.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_bootloader_image.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_busswitch.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_bus_keeper.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_cfs.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_cpu.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_cpu_alu.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_cpu_bus.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_cpu_control.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_cpu_cp_fpu.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_cpu_cp_bitmanip.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_cpu_cp_muldiv.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_cpu_cp_shifter.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_cpu_decompressor.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_cpu_regfile.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_debug_dm.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_debug_dtm.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_fifo.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_gpio.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_gptmr.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_icache.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_mtime.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_neoled.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_package.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_pwm.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_spi.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_sysinfo.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_top.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_trng.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_twi.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_uart.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_wdt.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_wishbone.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_xirq.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_dmem.entity.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="../../../rtl/core/neorv32_imem.entity.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="neorv32_dmem.ice40up_spram.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="neorv32_imem.ice40up_spram.vhd" type="VHDL" type_short="VHDL">
<Options lib="neorv32"/>
</Source>
<Source name="neorv32_upduino_v3_top.vhd" type="VHDL" type_short="VHDL">
<Options lib="work" top_module="neorv32_upduino_v3_top"/>
</Source>
<Source name="system_pll/system_pll.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
<Source name="neorv32_upduino_v3.pdc" type="Physical Constraints File" type_short="PDC">
<Options/>
</Source>
<Source name="source/impl_1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="neorv32_upduino_v3.sty"/>
</RadiantProject>

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-- #################################################################################################
-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
library work;
use work.all;
library iCE40UP;
use iCE40UP.components.all; -- for device primitives
entity neorv32_upduino_v3_top is
port (
-- UART (uart0) --
uart_txd_o : out std_ulogic;
uart_rxd_i : in std_ulogic;
-- SPI to on-board flash --
flash_sck_o : out std_ulogic;
flash_sdo_o : out std_ulogic;
flash_sdi_i : in std_ulogic;
flash_csn_o : out std_ulogic; -- NEORV32.SPI_CS(0)
-- SPI to IO pins --
spi_sck_o : out std_ulogic;
spi_sdo_o : out std_ulogic;
spi_sdi_i : in std_ulogic;
spi_csn_o : out std_ulogic; -- NEORV32.SPI_CS(1)
-- TWI --
twi_sda_io : inout std_logic;
twi_scl_io : inout std_logic;
-- GPIO --
gpio_i : in std_ulogic_vector(3 downto 0);
gpio_o : out std_ulogic_vector(3 downto 0);
-- PWM (to on-board RGB power LED) --
pwm_o : out std_ulogic_vector(2 downto 0)
);
end neorv32_upduino_v3_top;
architecture neorv32_upduino_v3_top_rtl of neorv32_upduino_v3_top is
-- configuration --
constant f_clock_c : natural := 24000000; -- PLL output clock frequency in Hz
-- On-chip oscillator --
signal hf_osc_clk : std_logic;
-- PLL (macro generated by radiant) --
component system_pll
port (
ref_clk_i : in std_logic;
rst_n_i : in std_logic;
lock_o : out std_logic;
outcore_o : out std_logic;
outglobal_o : out std_logic
);
end component;
signal pll_rstn : std_logic;
signal pll_clk : std_logic;
-- CPU --
signal cpu_clk : std_ulogic;
signal cpu_rstn : std_ulogic;
-- internal IO connection --
signal con_pwm : std_ulogic_vector(02 downto 0);
signal con_spi_sck : std_ulogic;
signal con_spi_sdi : std_ulogic;
signal con_spi_sdo : std_ulogic;
signal con_spi_csn : std_ulogic_vector(07 downto 0);
signal con_gpio_i : std_ulogic_vector(63 downto 0);
signal con_gpio_o : std_ulogic_vector(63 downto 0);
-- Misc --
signal pwm_drive : std_logic_vector(2 downto 0);
signal pwm_driven : std_ulogic_vector(2 downto 0);
begin
-- On-Chip HF Oscillator ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
HSOSC_inst : HSOSC
generic map (
CLKHF_DIV => "0b01" -- 24 MHz
)
port map (
CLKHFPU => '1',
CLKHFEN => '1',
CLKHF => hf_osc_clk
);
-- System PLL -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
system_pll_inst: system_pll
port map (
ref_clk_i => hf_osc_clk,
rst_n_i => '1',
lock_o => pll_rstn,
outcore_o => open,
outglobal_o => pll_clk
);
cpu_clk <= std_ulogic(pll_clk);
cpu_rstn <= std_ulogic(pll_rstn);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: neorv32_top
generic map (
-- General --
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
HW_THREAD_ID => 0, -- hardware thread id (32-bit)
INT_BOOTLOADER_EN => true, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A => true, -- implement atomic extension?
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters?
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
-- Extension Options --
CPU_CNT_WIDTH => 34, -- total width of CPU cycle and instret counters (0..64)
-- Internal Instruction memory --
MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => 64*1024, -- size of processor-internal instruction memory in bytes
-- Internal Data memory --
MEM_INT_DMEM_EN => true, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => 64*1024, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_SPI_EN => true, -- implement serial peripheral interface (SPI)?
IO_TWI_EN => true, -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH => 3, -- number of PWM channels to implement (0..60); 0 = disabled
IO_WDT_EN => true, -- implement watch dog timer (WDT)?
IO_TRNG_EN => true -- implement true random number generator (TRNG)?
)
port map (
-- Global control --
clk_i => cpu_clk, -- global clock, rising edge
rstn_i => cpu_rstn, -- global reset, low-active, async
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o => con_gpio_o, -- parallel output
gpio_i => con_gpio_i, -- parallel input
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o => uart_txd_o, -- UART0 send data
uart0_rxd_i => uart_rxd_i, -- UART0 receive data
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o => con_spi_sck,
spi_sdo_o => con_spi_sdo,
spi_sdi_i => con_spi_sdi,
spi_csn_o => con_spi_csn,
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io => twi_sda_io, -- twi serial data line
twi_scl_io => twi_scl_io, -- twi serial clock line
-- PWM (available if IO_PWM_EN = true) --
pwm_o => con_pwm -- pwm channels
);
-- GPIO --
con_gpio_i <= x"000000000000000" & gpio_i(3 downto 0);
gpio_o(3 downto 0) <= con_gpio_o(3 downto 0);
-- SPI --
flash_sck_o <= con_spi_sck;
flash_sdo_o <= con_spi_sdo;
flash_csn_o <= con_spi_csn(0);
spi_sck_o <= con_spi_sck;
spi_sdo_o <= con_spi_sdo;
spi_csn_o <= con_spi_csn(1);
con_spi_sdi <= flash_sdi_i when (con_spi_csn(0) = '0') else spi_sdi_i;
-- RGB --
pwm_drive(0) <= std_logic(con_pwm(0) or con_gpio_o(0)); -- bit 0: red - pwm channel 0 OR gpio_o(0) [status LED]
pwm_drive(1) <= std_logic(con_pwm(1)); -- bit 1: green - pwm channel 1
pwm_drive(2) <= std_logic(con_pwm(2)); -- bit 2: blue - pwm channel 2
RGB_inst: RGB
generic map (
CURRENT_MODE => "1",
RGB0_CURRENT => "0b000001",
RGB1_CURRENT => "0b000001",
RGB2_CURRENT => "0b000001"
)
port map (
CURREN => '1', -- I
RGBLEDEN => '1', -- I
RGB0PWM => pwm_drive(1), -- I - green
RGB1PWM => pwm_drive(2), -- I - blue
RGB2PWM => pwm_drive(0), -- I - red
RGB2 => pwm_driven(2), -- O - red
RGB1 => pwm_driven(1), -- O - blue
RGB0 => pwm_driven(0) -- O - green
);
pwm_o <= std_ulogic_vector(pwm_driven);
end neorv32_upduino_v3_top_rtl;

108
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<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="R3.0">
<Comment></Comment>
<Chain>
<Comm>SPI</Comm>
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>iCE40 UltraPlus</Family>
<Name>iCE40UP5K</Name>
<Package>All</Package>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>../../impl_1/neorv32_upduino_v3_impl_1.bin</File>
<FileTime>11/04/21 21:44:40</FileTime>
<MemoryType>External SPI Flash Memory (SPI FLASH)</MemoryType>
<Operation>Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<SVFProcessor>SVF Processor</SVFProcessor>
<AccessMode>Direct Programming</AccessMode>
</Option>
<FPGALoader>
<CPLDDevice>
<Device>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>iCE40 UltraPlus</Family>
<Name>iCE40UP5K</Name>
<IDCode>0x11200639</IDCode>
<Package>All</Package>
<PON>iCE40UP5K</PON>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<MemoryType>Compressed Random Access Memory (CRAM)</MemoryType>
<Operation>Bypass</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<IOVectorData></IOVectorData>
<SVFProcessor>SVF Processor</SVFProcessor>
<AccessMode>Direct Programming</AccessMode>
</Option>
</Device>
</CPLDDevice>
<FlashDevice>
<Device>
<Pos>1</Pos>
<Vendor>WinBond</Vendor>
<Family>SPI Serial Flash</Family>
<Name>W25Q32</Name>
<IDCode>0x15</IDCode>
<Package>8-pin SOIC</Package>
<Operation>Erase,Program,Verify</Operation>
<File>../../impl_1/neorv32_upduino_v3_impl_1.bin</File>
<AddressBase>0x00000000</AddressBase>
<EndAddress>0x003F0000</EndAddress>
<DeviceSize>32</DeviceSize>
<DataSize>104156</DataSize>
<NumberOfDevices>1</NumberOfDevices>
<ReInitialize value="FALSE"/>
</Device>
</FlashDevice>
<FPGADevice>
<Device>
<Pos>1</Pos>
<Name></Name>
<File>N:/Projects/neorv32/boards/UPduino_v3/impl_1/neorv32_upduino_v3_impl_1.bin</File>
<LocalChainList>
<LocalDevice index="-99"
name="Unknown"
file="N:/Projects/neorv32/boards/UPduino_v3/impl_1/neorv32_upduino_v3_impl_1.bin"/>
</LocalChainList>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<SVFProcessor>SVF Processor</SVFProcessor>
</Option>
</Device>
</FPGADevice>
</FPGALoader>
</Device>
</Chain>
<ProjectOptions>
<Program>SEQUENTIAL</Program>
<Process>ENTIRED CHAIN</Process>
<OperationOverride>No Override</OperationOverride>
<StartTAP>TLR</StartTAP>
<EndTAP>TLR</EndTAP>
<DisableCheckBoard value="TRUE"/>
<VerifyUsercode value="FALSE"/>
<TCKDelay>1</TCKDelay>
</ProjectOptions>
<CableOptions>
<CableName>USB2</CableName>
<PortAdd>FTUSB-1</PortAdd>
<USBID>UPduino v3.0 Location 0002 Serial </USBID>
</CableOptions>
</ispXCF>

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Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/system_pll/rtl/system_pll.v Normal file
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/*******************************************************************************
Verilog netlist generated by IPGEN Lattice Radiant Software (64-bit)
2.1.0.27.2
Soft IP Version: 1.0.1
Wed May 12 22:58:47 2021
*******************************************************************************/
/*******************************************************************************
Wrapper Module generated per user settings.
*******************************************************************************/
module system_pll (ref_clk_i,
rst_n_i,
lock_o,
outcore_o,
outglobal_o) ;
input ref_clk_i ;
input rst_n_i ;
output lock_o ;
output outcore_o ;
output outglobal_o ;
system_pll_ipgen_lscc_pll #(.DIVR("0"),
.FILTER_RANGE("2"),
.FREQUENCY_PIN_REFERENCECLK("24.000000"),
.FEEDBACK_PATH("PHASE_AND_DELAY"),
.EXTERNAL_DIVIDE_FACTOR("NONE"),
.DIVF("0"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.FDA_FEEDBACK("0"),
.SHIFTREG_DIV_MODE("0"),
.PLLOUT_SELECT_PORTA("SHIFTREG_0deg"),
.PLLOUT_SELECT_PORTB("SHIFTREG_0deg"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.FDA_RELATIVE("0"),
.DIVQ("3"),
.ENABLE_ICEGATE_PORTA("0"),
.ENABLE_ICEGATE_PORTB("0")) lscc_pll_inst (.ref_clk_i(ref_clk_i),
.rst_n_i(rst_n_i),
.feedback_i(1'b0),
.dynamic_delay_i({4'b0000,
4'b0000}),
.bypass_i(1'b0),
.latch_i(1'b0),
.lock_o(lock_o),
.outcore_o(outcore_o),
.outglobal_o(outglobal_o),
.outcoreb_o(),
.outglobalb_o(),
.sclk_i(),
.sdi_i(),
.sdo_o()) ;
endmodule
// =============================================================================
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// -----------------------------------------------------------------------------
// Copyright (c) 2017 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------------------
//
// Permission:
//
// Lattice SG Pte. Ltd. grants permission to use this code
// pursuant to the terms of the Lattice Reference Design License Agreement.
//
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Lattice provides no warranty
// regarding the use or functionality of this code.
//
// -----------------------------------------------------------------------------
//
// Lattice SG Pte. Ltd.
// 101 Thomson Road, United Square #07-02
// Singapore 307591
//
//
// TEL: 1-800-Lattice (USA and Canada)
// +65-6631-2000 (Singapore)
// +1-503-268-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: techsupport@latticesemi.com
//
// -----------------------------------------------------------------------------
//
// =============================================================================
// FILE DETAILS
// Project :
// File : lscc_pll.v
// Title :
// Dependencies : 1. PLL_B primitive
// Description : iCE40UP Phase-Locked Loop.
// =============================================================================
// REVISION HISTORY
// Version : 1.0.0.
// Author(s) :
// Mod. Date : 04.20.2017
// Changes Made : Initial release.
// =============================================================================
module system_pll_ipgen_lscc_pll #(parameter DIVR = "1",
parameter DIVF = "1",
parameter DIVQ = "1",
parameter FEEDBACK_PATH = "SIMPLE",
parameter FILTER_RANGE = "0",
parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED",
parameter FDA_FEEDBACK = "0",
parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED",
parameter FDA_RELATIVE = "0",
parameter SHIFTREG_DIV_MODE = "0",
parameter PLLOUT_SELECT_PORTA = "SHIFTREG_0deg",
parameter PLLOUT_SELECT_PORTB = "SHIFTREG_0deg",
parameter EXTERNAL_DIVIDE_FACTOR = "NONE",
parameter ENABLE_ICEGATE_PORTA = "0",
parameter ENABLE_ICEGATE_PORTB = "0",
parameter FREQUENCY_PIN_REFERENCECLK = "10.0") (
// -----------------------------------------------------------------------------
// Module Parameters
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
// Input/Output Ports
// -----------------------------------------------------------------------------
input ref_clk_i,
input rst_n_i,
input feedback_i,
input [7:0] dynamic_delay_i,
input bypass_i,
input latch_i,
output wire lock_o,
output wire outcore_o,
output wire outglobal_o,
output wire outcoreb_o,
output wire outglobalb_o,
input sclk_i,
input sdi_i,
output wire sdo_o) ;
// -----------------------------------------------------------------------------
// Wire Declarations
// -----------------------------------------------------------------------------
wire [7:0] dynamic_delay_w ;
wire feedback_w ;
wire intfbout_w ;
// -----------------------------------------------------------------------------
// Generate Assign Statements
// -----------------------------------------------------------------------------
generate
if ((EXTERNAL_DIVIDE_FACTOR != "NONE"))
begin : genblk1
assign feedback_w = feedback_i ;
end
else
begin : genblk1
assign feedback_w = intfbout_w ;
end
endgenerate
generate
if ((DELAY_ADJUSTMENT_MODE_FEEDBACK == "FIXED"))
begin : genblk2
assign dynamic_delay_w[3:0] = 4'b0 ;
end
else
begin : genblk2
assign dynamic_delay_w[3:0] = dynamic_delay_i[3:0] ;
end
if ((DELAY_ADJUSTMENT_MODE_RELATIVE == "FIXED"))
begin : genblk3
assign dynamic_delay_w[7:4] = 4'b0 ;
end
else
begin : genblk3
assign dynamic_delay_w[7:4] = dynamic_delay_i[7:4] ;
end
endgenerate
// -----------------------------------------------------------------------------
// PLL Primitive Instantiation
// -----------------------------------------------------------------------------
PLL_B #(.DIVR(DIVR),
.DIVF(DIVF),
.DIVQ(DIVQ),
.FEEDBACK_PATH(FEEDBACK_PATH),
.FILTER_RANGE(FILTER_RANGE),
.DELAY_ADJUSTMENT_MODE_FEEDBACK(DELAY_ADJUSTMENT_MODE_FEEDBACK),
.FDA_FEEDBACK(FDA_FEEDBACK),
.DELAY_ADJUSTMENT_MODE_RELATIVE(DELAY_ADJUSTMENT_MODE_RELATIVE),
.FDA_RELATIVE(FDA_RELATIVE),
.SHIFTREG_DIV_MODE(SHIFTREG_DIV_MODE),
.PLLOUT_SELECT_PORTA(PLLOUT_SELECT_PORTA),
.PLLOUT_SELECT_PORTB(PLLOUT_SELECT_PORTB),
.EXTERNAL_DIVIDE_FACTOR(EXTERNAL_DIVIDE_FACTOR),
.ENABLE_ICEGATE_PORTA(ENABLE_ICEGATE_PORTA),
.ENABLE_ICEGATE_PORTB(ENABLE_ICEGATE_PORTB),
.FREQUENCY_PIN_REFERENCECLK(FREQUENCY_PIN_REFERENCECLK)) u_PLL_B (.REFERENCECLK(ref_clk_i),
.RESET_N(rst_n_i),
.FEEDBACK(feedback_w),
.DYNAMICDELAY7(dynamic_delay_w[7]),
.DYNAMICDELAY6(dynamic_delay_w[6]),
.DYNAMICDELAY5(dynamic_delay_w[5]),
.DYNAMICDELAY4(dynamic_delay_w[4]),
.DYNAMICDELAY3(dynamic_delay_w[3]),
.DYNAMICDELAY2(dynamic_delay_w[2]),
.DYNAMICDELAY1(dynamic_delay_w[1]),
.DYNAMICDELAY0(dynamic_delay_w[0]),
.INTFBOUT(intfbout_w),
.BYPASS(bypass_i),
.LATCH(latch_i),
.OUTCORE(outcore_o),
.OUTGLOBAL(outglobal_o),
.OUTCOREB(outcoreb_o),
.OUTGLOBALB(outglobalb_o),
.LOCK(lock_o),
.SCLK(sclk_i),
.SDI(sdi_i),
.SDO(sdo_o)) ;
endmodule

12
Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/system_pll/system_pll.ipx Normal file
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@ -0,0 +1,12 @@
<?xml version="1.0" ?>
<RadiantModule architecture="iCE40UP" date="2021 05 12 22:58:47" device="iCE40UP5K" generator="ipgen" library="module" module="pll" name="system_pll" package="SG48" source_format="Verilog" speed="High-Performance_1.2V" vendor="latticesemi.com" version="1.0.1">
<Package>
<File modified="2021 05 12 22:58:47" name="rtl/system_pll_bb.v" type="black_box_verilog"/>
<File modified="2021 05 12 22:58:47" name="system_pll.cfg" type="cfg"/>
<File modified="2021 05 12 22:58:47" name="misc/system_pll_tmpl.v" type="template_verilog"/>
<File modified="2021 05 12 22:58:47" name="misc/system_pll_tmpl.vhd" type="template_vhdl"/>
<File modified="2021 05 12 22:58:47" name="rtl/system_pll.v" type="top_level_verilog"/>
<File modified="2021 05 12 22:58:47" name="component.xml" type="IP-XACT_component"/>
<File modified="2021 05 12 22:58:47" name="design.xml" type="IP-XACT_design"/>
</Package>
</RadiantModule>