Initial commit

Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/.gitignore

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+/vivado*
+/.Xil
+/work/*

Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/README.md

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+# NEORV32 Test Setup for the Digilent Nexys A7 and Nexys 4 DDR FPGA Boards
+
+This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Digilent Nexys A7 and Nexys 4 DDR boards.
+It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor
+top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs).
+
+* FPGA Boards:
+  * :books: [Digilent Nexys A7 FPGA Boards](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual)
+  * :books: [Digilent Nexys 4 DDR FPGA Board](https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/reference-manual)
+* FPGAs:
+  * Xilinx Artix-7 `XC7A50TCSG324-1`
+  * Xilinx Artix-7 `XC7A100TCSG324-1`
+* Toolchain: Xilinx Vivado (tested with Vivado 2020.2)
+
+
+## NEORV32 Configuration
+
+:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for
+configuration and entity details and [`nexys_a7_test_setup.xdc`](https://github.com/AWenzel83/neorv32/blob/nexys_a7_example/boards/nexys-a7-test-setup/nexys_a7_test_setup.xdc)
+for the according FPGA pin mapping.
+
+* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors)
+* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM
+* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT`
+* Tested with version [`1.5.3.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
+* Clock: 100MHz from on-board oscillator
+* Reset: Via dedicated on-board "RESET" button
+* GPIO output port `gpio_o` bits 0..7 are connected to the green on-board LEDs (LD0 - LD7); LD0 is the bootloader status LED
+* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board USB-UART chip

Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/create_project.tcl

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+set board "A7-50"
+
+# create and clear output directory
+set outputdir work
+file mkdir $outputdir
+
+set files [glob -nocomplain "$outputdir/*"]
+if {[llength $files] != 0} {
+    puts "deleting contents of $outputdir"
+    file delete -force {*}[glob -directory $outputdir *]; # clear folder contents
+} else {
+    puts "$outputdir is empty"
+}
+
+switch $board {
+  "A7-50" {
+    set a7part "xc7a50tcsg324-1"
+    set a7prj "nexys-a7-50-test-setup"
+  }
+  "A7-100" {
+    set a7part "xc7a100tcsg324-1"
+    set a7prj "nexys-a7-100-test-setup"
+  }
+}
+
+# create project
+create_project -part $a7part $a7prj $outputdir
+
+# add source files: core sources
+add_files [glob ./../../../rtl/core/*.vhd] ./../../../rtl/core/mem/neorv32_dmem.default.vhd ./../../../rtl/core/mem/neorv32_imem.default.vhd
+set_property library neorv32 [get_files [glob ./../../../rtl/core/*.vhd]]
+set_property library neorv32 [get_files [glob ./../../../rtl/core/mem/neorv32_*mem.default.vhd]]
+
+# add source file: top entity
+add_files [glob ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd]
+
+# add source files: simulation-only
+add_files -fileset sim_1 [list ./../../../sim/simple/neorv32_tb.simple.vhd ./../../../sim/simple/uart_rx.simple.vhd]
+
+# add source files: constraints
+add_files -fileset constrs_1 [glob ./*.xdc]
+
+# run synthesis, implementation and bitstream generation
+launch_runs impl_1 -to_step write_bitstream -jobs 4
+wait_on_run impl_1

Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/nexys_a7_test_setup.xdc

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+## This file is a general .xdc for the Nexys A7 and Nexys 4 DDR
+## For default neorv32_test_setup.vhd top entity
+
+## Clock signal
+set_property -dict { PACKAGE_PIN E3   IOSTANDARD LVCMOS33 } [get_ports { clk_i }]; 	   #IO_L12P_T1_MRCC_35 	  Sch=gclk[100]
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk_i }];
+
+## LEDs
+set_property -dict { PACKAGE_PIN H17  IOSTANDARD LVCMOS33 } [get_ports { gpio_o[0] }]; #IO_L18P_T2_A24_15 	  Sch=led[0]
+set_property -dict { PACKAGE_PIN K15  IOSTANDARD LVCMOS33 } [get_ports { gpio_o[1] }]; #IO_L24P_T3_RS1_15 	  Sch=led[1]
+set_property -dict { PACKAGE_PIN J13  IOSTANDARD LVCMOS33 } [get_ports { gpio_o[2] }]; #IO_L17N_T2_A25_15 	  Sch=led[2]
+set_property -dict { PACKAGE_PIN N14  IOSTANDARD LVCMOS33 } [get_ports { gpio_o[3] }]; #IO_L8P_T1_D11_14  	  Sch=led[3]
+set_property -dict { PACKAGE_PIN R18  IOSTANDARD LVCMOS33 } [get_ports { gpio_o[4] }]; #IO_L7P_T1_D09_14      Sch=led[4]
+set_property -dict { PACKAGE_PIN V17  IOSTANDARD LVCMOS33 } [get_ports { gpio_o[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
+set_property -dict { PACKAGE_PIN U17  IOSTANDARD LVCMOS33 } [get_ports { gpio_o[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
+set_property -dict { PACKAGE_PIN U16  IOSTANDARD LVCMOS33 } [get_ports { gpio_o[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
+
+## USB-UART Interface
+set_property -dict { PACKAGE_PIN D4  IOSTANDARD LVCMOS33 } [get_ports { uart0_txd_o }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
+set_property -dict { PACKAGE_PIN C4  IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd_i }]; #IO_L7P_T1_AD6P_35 	Sch=uart_txd_in
+
+## Misc.
+set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { rstn_i }];     #IO_L3P_T0_DQS_AD1P_15 Sch=ck_rst