add square signal
This commit is contained in:
parent
95e3c95a06
commit
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@ -0,0 +1,55 @@
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@ -1279,6 +1279,7 @@ projectPaths [
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"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\01-WaveformGenerator\\Prefs\\hds.hdp"
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"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\01-WaveformGenerator\\Prefs\\hds.hdp"
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"C:\\work\\edu\\sem\\labo\\sem_labs\\01-WaveformGenerator\\Prefs\\hds.hdp"
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"C:\\work\\edu\\sem\\labo\\sem_labs\\01-WaveformGenerator\\Prefs\\hds.hdp"
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"C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\hds.hdp"
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"C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\hds.hdp"
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"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\hds.hdp"
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exportPageSetupInfo (PageSetupInfo
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@ -4291,7 +4148,7 @@ hdsWorkspaceLocation ""
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relativeLibraryRootDir ""
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relativeLibraryRootDir ""
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vmLabelLatestDontAskAgain 0
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vmLabelLatestDontAskAgain 0
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6841
01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs.bak
Normal file
6841
01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs.bak
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,28 @@
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-- VHDL Entity WaveformGenerator.lowpass.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 08:02:49 03/11/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY lowpass IS
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GENERIC(
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||||||
|
signalBitNb : positive := 16;
|
||||||
|
shiftBitNb : positive := 12
|
||||||
|
);
|
||||||
|
PORT(
|
||||||
|
lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
clock : IN std_ulogic;
|
||||||
|
reset : IN std_ulogic;
|
||||||
|
lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END lowpass ;
|
||||||
|
|
||||||
@ -1,4 +1,16 @@
|
|||||||
ARCHITECTURE studentVersion OF sawtoothToSquare IS
|
ARCHITECTURE studentVersion OF sawtoothToSquare IS
|
||||||
|
|
||||||
|
signal mySignal : unsigned(bitNb-1 downto 0);
|
||||||
|
constant constOf0 : unsigned(bitNb-2 downto 0) := (others => '0');
|
||||||
|
constant myConst : unsigned(bitNb-1 downto 0) := ('1' & constOf0);
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
square <= (others => '0');
|
|
||||||
|
convert: process(sawtooth)
|
||||||
|
begin
|
||||||
|
mySignal <= sawtooth AND myConst;
|
||||||
|
end process convert;
|
||||||
|
|
||||||
|
square <= (others => sawtooth(bitNb-1));
|
||||||
|
|
||||||
END ARCHITECTURE studentVersion;
|
END ARCHITECTURE studentVersion;
|
||||||
|
|||||||
@ -0,0 +1,28 @@
|
|||||||
|
-- VHDL Entity WaveformGenerator.sawtoothGen.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - francois.francois (Aphelia)
|
||||||
|
-- at - 08:02:49 03/11/19
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
ENTITY sawtoothGen IS
|
||||||
|
GENERIC(
|
||||||
|
bitNb : positive := 16
|
||||||
|
);
|
||||||
|
PORT(
|
||||||
|
sawtooth : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||||
|
clock : IN std_ulogic;
|
||||||
|
reset : IN std_ulogic;
|
||||||
|
step : IN unsigned (bitNb-1 DOWNTO 0);
|
||||||
|
en : IN std_ulogic
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END sawtoothGen ;
|
||||||
|
|
||||||
@ -0,0 +1,25 @@
|
|||||||
|
-- VHDL Entity WaveformGenerator.sawtoothToSquare.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - francois.francois (Aphelia)
|
||||||
|
-- at - 08:02:49 03/11/19
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
ENTITY sawtoothToSquare IS
|
||||||
|
GENERIC(
|
||||||
|
bitNb : positive := 16
|
||||||
|
);
|
||||||
|
PORT(
|
||||||
|
square : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||||
|
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END sawtoothToSquare ;
|
||||||
|
|
||||||
@ -0,0 +1,25 @@
|
|||||||
|
-- VHDL Entity WaveformGenerator.sawtoothToTriangle.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - francois.francois (Aphelia)
|
||||||
|
-- at - 08:02:49 03/11/19
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
ENTITY sawtoothToTriangle IS
|
||||||
|
GENERIC(
|
||||||
|
bitNb : positive := 16
|
||||||
|
);
|
||||||
|
PORT(
|
||||||
|
triangle : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||||
|
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END sawtoothToTriangle ;
|
||||||
|
|
||||||
@ -0,0 +1,25 @@
|
|||||||
|
-- VHDL Entity WaveformGenerator.triangleToPolygon.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - francois.francois (Aphelia)
|
||||||
|
-- at - 08:02:49 03/11/19
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
ENTITY triangleToPolygon IS
|
||||||
|
GENERIC(
|
||||||
|
bitNb : positive := 16
|
||||||
|
);
|
||||||
|
PORT(
|
||||||
|
polygon : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||||
|
triangle : IN unsigned (bitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END triangleToPolygon ;
|
||||||
|
|
||||||
@ -0,0 +1,33 @@
|
|||||||
|
-- VHDL Entity WaveformGenerator.waveformGen.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - francois.corthay.UNKNOWN (WEA20303)
|
||||||
|
-- at - 17:19:13 06.03.2019
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
ENTITY waveformGen IS
|
||||||
|
GENERIC(
|
||||||
|
phaseBitNb : positive := 16;
|
||||||
|
signalBitNb : positive := 16
|
||||||
|
);
|
||||||
|
PORT(
|
||||||
|
clock : IN std_ulogic;
|
||||||
|
en : IN std_ulogic;
|
||||||
|
reset : IN std_ulogic;
|
||||||
|
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
|
||||||
|
polygon : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
sawtooth : OUT unsigned (phaseBitNb-1 DOWNTO 0);
|
||||||
|
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END waveformGen ;
|
||||||
|
|
||||||
@ -0,0 +1,146 @@
|
|||||||
|
--
|
||||||
|
-- VHDL Architecture WaveformGenerator.waveformGen.struct
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - axel.amand.UNKNOWN (WE7860)
|
||||||
|
-- at - 14:40:08 28.04.2023
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
LIBRARY WaveformGenerator;
|
||||||
|
|
||||||
|
ARCHITECTURE struct OF waveformGen IS
|
||||||
|
|
||||||
|
-- Architecture declarations
|
||||||
|
|
||||||
|
-- Internal signal declarations
|
||||||
|
|
||||||
|
-- Implicit buffer signal declarations
|
||||||
|
SIGNAL polygon_internal : unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
SIGNAL sawtooth_internal : unsigned (phaseBitNb-1 DOWNTO 0);
|
||||||
|
SIGNAL triangle_internal : unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
|
||||||
|
|
||||||
|
-- Component Declarations
|
||||||
|
COMPONENT lowpass
|
||||||
|
GENERIC (
|
||||||
|
signalBitNb : positive := 16;
|
||||||
|
shiftBitNb : positive := 12
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
clock : IN std_ulogic ;
|
||||||
|
reset : IN std_ulogic ;
|
||||||
|
lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
COMPONENT sawtoothGen
|
||||||
|
GENERIC (
|
||||||
|
bitNb : positive := 16
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
sawtooth : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||||
|
clock : IN std_ulogic ;
|
||||||
|
reset : IN std_ulogic ;
|
||||||
|
step : IN unsigned (bitNb-1 DOWNTO 0);
|
||||||
|
en : IN std_ulogic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
COMPONENT sawtoothToSquare
|
||||||
|
GENERIC (
|
||||||
|
bitNb : positive := 16
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
square : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||||
|
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
COMPONENT sawtoothToTriangle
|
||||||
|
GENERIC (
|
||||||
|
bitNb : positive := 16
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
triangle : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||||
|
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
COMPONENT triangleToPolygon
|
||||||
|
GENERIC (
|
||||||
|
bitNb : positive := 16
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
polygon : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||||
|
triangle : IN unsigned (bitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
-- Optional embedded configurations
|
||||||
|
-- pragma synthesis_off
|
||||||
|
FOR ALL : lowpass USE ENTITY WaveformGenerator.lowpass;
|
||||||
|
FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen;
|
||||||
|
FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare;
|
||||||
|
FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle;
|
||||||
|
FOR ALL : triangleToPolygon USE ENTITY WaveformGenerator.triangleToPolygon;
|
||||||
|
-- pragma synthesis_on
|
||||||
|
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
|
||||||
|
-- Instance port mappings.
|
||||||
|
I_lp : lowpass
|
||||||
|
GENERIC MAP (
|
||||||
|
signalBitNb => signalBitNb,
|
||||||
|
shiftBitNb => 10
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
lowpassOut => sine,
|
||||||
|
clock => clock,
|
||||||
|
reset => reset,
|
||||||
|
lowpassIn => polygon_internal
|
||||||
|
);
|
||||||
|
I_saw : sawtoothGen
|
||||||
|
GENERIC MAP (
|
||||||
|
bitNb => phaseBitNb
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
sawtooth => sawtooth_internal,
|
||||||
|
clock => clock,
|
||||||
|
reset => reset,
|
||||||
|
step => step,
|
||||||
|
en => en
|
||||||
|
);
|
||||||
|
I_square : sawtoothToSquare
|
||||||
|
GENERIC MAP (
|
||||||
|
bitNb => signalBitNb
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
square => square,
|
||||||
|
sawtooth => sawtooth_internal
|
||||||
|
);
|
||||||
|
I_tri : sawtoothToTriangle
|
||||||
|
GENERIC MAP (
|
||||||
|
bitNb => signalBitNb
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
triangle => triangle_internal,
|
||||||
|
sawtooth => sawtooth_internal
|
||||||
|
);
|
||||||
|
I_poly : triangleToPolygon
|
||||||
|
GENERIC MAP (
|
||||||
|
bitNb => signalBitNb
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
polygon => polygon_internal,
|
||||||
|
triangle => triangle_internal
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Implicit buffered output assignments
|
||||||
|
polygon <= polygon_internal;
|
||||||
|
sawtooth <= sawtooth_internal;
|
||||||
|
triangle <= triangle_internal;
|
||||||
|
|
||||||
|
END struct;
|
||||||
@ -0,0 +1,27 @@
|
|||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 50,0 8 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 13,0 13 1
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 18 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 19 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 76,0 20 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 83,0 21 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 24 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 25 0
|
||||||
@ -0,0 +1,30 @@
|
|||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 50,0 8 0
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 13,0 13 1
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 17 0
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 18 0
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 76,0 19 0
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 83,0 20 0
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 89,0 21 0
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 24 0
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 25 0
|
||||||
@ -0,0 +1,21 @@
|
|||||||
|
DESIGN sawtooth@to@square
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN sawtooth@to@square
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 50,0 8 0
|
||||||
|
DESIGN sawtooth@to@square
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 13,0 13 1
|
||||||
|
DESIGN sawtooth@to@square
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 17 0
|
||||||
|
DESIGN sawtooth@to@square
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 83,0 18 0
|
||||||
|
DESIGN sawtooth@to@square
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 21 0
|
||||||
|
DESIGN sawtooth@to@square
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 22 0
|
||||||
@ -0,0 +1,21 @@
|
|||||||
|
DESIGN sawtooth@to@triangle
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN sawtooth@to@triangle
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 50,0 8 0
|
||||||
|
DESIGN sawtooth@to@triangle
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 13,0 13 1
|
||||||
|
DESIGN sawtooth@to@triangle
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 17 0
|
||||||
|
DESIGN sawtooth@to@triangle
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 83,0 18 0
|
||||||
|
DESIGN sawtooth@to@triangle
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 21 0
|
||||||
|
DESIGN sawtooth@to@triangle
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 22 0
|
||||||
@ -0,0 +1,21 @@
|
|||||||
|
DESIGN triangle@to@polygon
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN triangle@to@polygon
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 50,0 8 0
|
||||||
|
DESIGN triangle@to@polygon
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 13,0 13 1
|
||||||
|
DESIGN triangle@to@polygon
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 17 0
|
||||||
|
DESIGN triangle@to@polygon
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 83,0 18 0
|
||||||
|
DESIGN triangle@to@polygon
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 21 0
|
||||||
|
DESIGN triangle@to@polygon
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 22 0
|
||||||
@ -0,0 +1,42 @@
|
|||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 50,0 8 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 13,0 13 1
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 18 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 123,0 19 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 88,0 20 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 113,0 21 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 93,0 22 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 98,0 23 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 103,0 24 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 108,0 25 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 118,0 26 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 29 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 30 0
|
||||||
@ -0,0 +1,215 @@
|
|||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 84,0 9 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 12
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 0,0 15 2
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 20
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 513,0 22 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 414,0 23 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 424,0 24 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 26
|
||||||
|
LIBRARY WaveformGenerator
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW student@version
|
||||||
|
GRAPHIC 1036,0 28 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 14,0 29 1
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 34 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 35 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 76,0 36 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 83,0 37 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1227,0 40 0
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 14,0 41 1
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 45 0
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 46 0
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 76,0 47 0
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 83,0 48 0
|
||||||
|
DESIGN sawtooth@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 89,0 49 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 916,0 52 0
|
||||||
|
DESIGN sawtooth@to@square
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 14,0 53 1
|
||||||
|
DESIGN sawtooth@to@square
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 57 0
|
||||||
|
DESIGN sawtooth@to@square
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 83,0 58 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 977,0 61 0
|
||||||
|
DESIGN sawtooth@to@triangle
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 14,0 62 1
|
||||||
|
DESIGN sawtooth@to@triangle
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 66 0
|
||||||
|
DESIGN sawtooth@to@triangle
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 83,0 67 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1011,0 70 0
|
||||||
|
DESIGN triangle@to@polygon
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 14,0 71 1
|
||||||
|
DESIGN triangle@to@polygon
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 75 0
|
||||||
|
DESIGN triangle@to@polygon
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 83,0 76 0
|
||||||
|
LIBRARY WaveformGenerator
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 79
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1036,0 82 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1227,0 83 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 916,0 84 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 977,0 85 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1011,0 86 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 89
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 91
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1036,0 93 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1043,0 94 1
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 562,0 99 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 184,0 100 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 192,0 101 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 513,0 102 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1227,0 104 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1234,0 105 1
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 414,0 109 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 15,0 110 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 237,0 111 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 319,0 112 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 719,0 113 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 916,0 115 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 923,0 116 1
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 480,0 120 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 414,0 121 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 977,0 123 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 984,0 124 1
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 424,0 128 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 472,0 129 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1011,0 131 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1018,0 132 1
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 513,0 136 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 424,0 137 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 513,0 141 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 414,0 142 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 424,0 143 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 145
|
||||||
@ -0,0 +1,6 @@
|
|||||||
|
EDIT_LOCK
|
||||||
|
remi.heredero
|
||||||
|
UNKNOWN
|
||||||
|
WE2330808
|
||||||
|
2208
|
||||||
|
27.02.2024-10:16:57.263000
|
||||||
@ -0,0 +1,15 @@
|
|||||||
|
-- VHDL Entity WaveformGenerator_test.waveformGen_tb.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - francois.corthay.UNKNOWN (WEA30906)
|
||||||
|
-- at - 14:48:16 25.02.2019
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY waveformGen_tb IS
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END waveformGen_tb ;
|
||||||
|
|
||||||
@ -0,0 +1,106 @@
|
|||||||
|
--
|
||||||
|
-- VHDL Architecture WaveformGenerator_test.waveformGen_tb.struct
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - remi.heredero.UNKNOWN (WE2330808)
|
||||||
|
-- at - 11:05:34 27.02.2024
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
LIBRARY WaveformGenerator;
|
||||||
|
LIBRARY WaveformGenerator_test;
|
||||||
|
|
||||||
|
ARCHITECTURE struct OF waveformGen_tb IS
|
||||||
|
|
||||||
|
-- Architecture declarations
|
||||||
|
constant bitNb: positive := 16;
|
||||||
|
constant clockFrequency: real := 60.0E6;
|
||||||
|
--constant clockFrequency: real := 66.0E6;
|
||||||
|
|
||||||
|
-- Internal signal declarations
|
||||||
|
SIGNAL clock : std_ulogic;
|
||||||
|
SIGNAL en : std_ulogic;
|
||||||
|
SIGNAL reset : std_ulogic;
|
||||||
|
SIGNAL sawtooth : unsigned(bitNb-1 DOWNTO 0);
|
||||||
|
SIGNAL square : unsigned(bitNb-1 DOWNTO 0);
|
||||||
|
SIGNAL step : unsigned(bitNb-1 DOWNTO 0);
|
||||||
|
|
||||||
|
|
||||||
|
-- Component Declarations
|
||||||
|
COMPONENT waveformGen
|
||||||
|
GENERIC (
|
||||||
|
phaseBitNb : positive := 16;
|
||||||
|
signalBitNb : positive := 16
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
clock : IN std_ulogic ;
|
||||||
|
en : IN std_ulogic ;
|
||||||
|
reset : IN std_ulogic ;
|
||||||
|
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
|
||||||
|
polygon : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
sawtooth : OUT unsigned (phaseBitNb-1 DOWNTO 0);
|
||||||
|
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
COMPONENT waveformGen_tester
|
||||||
|
GENERIC (
|
||||||
|
bitNb : positive := 16;
|
||||||
|
clockFrequency : real := 60.0E6
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
sawtooth : IN unsigned (bitNb-1 DOWNTO 0);
|
||||||
|
square : IN unsigned (bitNb-1 DOWNTO 0);
|
||||||
|
clock : OUT std_ulogic ;
|
||||||
|
en : OUT std_ulogic ;
|
||||||
|
reset : OUT std_ulogic ;
|
||||||
|
step : OUT unsigned (bitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
-- Optional embedded configurations
|
||||||
|
-- pragma synthesis_off
|
||||||
|
FOR ALL : waveformGen USE ENTITY WaveformGenerator.waveformGen;
|
||||||
|
FOR ALL : waveformGen_tester USE ENTITY WaveformGenerator_test.waveformGen_tester;
|
||||||
|
-- pragma synthesis_on
|
||||||
|
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
|
||||||
|
-- Instance port mappings.
|
||||||
|
I_DUT : waveformGen
|
||||||
|
GENERIC MAP (
|
||||||
|
phaseBitNb => bitNb,
|
||||||
|
signalBitNb => bitNb
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
clock => clock,
|
||||||
|
en => en,
|
||||||
|
reset => reset,
|
||||||
|
step => step,
|
||||||
|
polygon => OPEN,
|
||||||
|
sawtooth => sawtooth,
|
||||||
|
sine => OPEN,
|
||||||
|
square => square,
|
||||||
|
triangle => OPEN
|
||||||
|
);
|
||||||
|
I_tb : waveformGen_tester
|
||||||
|
GENERIC MAP (
|
||||||
|
bitNb => bitNb,
|
||||||
|
clockFrequency => clockFrequency
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
sawtooth => sawtooth,
|
||||||
|
square => square,
|
||||||
|
clock => clock,
|
||||||
|
en => en,
|
||||||
|
reset => reset,
|
||||||
|
step => step
|
||||||
|
);
|
||||||
|
|
||||||
|
END struct;
|
||||||
@ -0,0 +1,30 @@
|
|||||||
|
-- VHDL Entity WaveformGenerator_test.waveformGen_tester.interface
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - remi.heredero.UNKNOWN (WE2330808)
|
||||||
|
-- at - 11:05:34 27.02.2024
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
ENTITY waveformGen_tester IS
|
||||||
|
GENERIC(
|
||||||
|
bitNb : positive := 16;
|
||||||
|
clockFrequency : real := 60.0E6
|
||||||
|
);
|
||||||
|
PORT(
|
||||||
|
sawtooth : IN unsigned (BitNb-1 DOWNTO 0);
|
||||||
|
square : IN unsigned (BitNb-1 DOWNTO 0);
|
||||||
|
clock : OUT std_ulogic;
|
||||||
|
en : OUT std_ulogic;
|
||||||
|
reset : OUT std_ulogic;
|
||||||
|
step : OUT unsigned (bitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END waveformGen_tester ;
|
||||||
|
|
||||||
@ -0,0 +1,12 @@
|
|||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 50,0 8 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 11 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 12 0
|
||||||
@ -0,0 +1,150 @@
|
|||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 142,0 9 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 12
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 0,0 16 2
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1,0 19 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 19
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 53,0 24 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 700,0 25 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 45,0 26 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1180,0 27 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1263,0 28 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 594,0 29 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 30
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 31
|
||||||
|
LIBRARY WaveformGenerator
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW struct
|
||||||
|
GRAPHIC 954,0 33 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 14,0 34 1
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 39 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 123,0 40 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 88,0 41 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 113,0 42 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 93,0 43 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 98,0 44 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 103,0 45 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 108,0 46 0
|
||||||
|
DESIGN waveform@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 118,0 47 0
|
||||||
|
LIBRARY WaveformGenerator_test
|
||||||
|
DESIGN waveform@gen_tester
|
||||||
|
VIEW test
|
||||||
|
GRAPHIC 421,0 50 0
|
||||||
|
DESIGN waveform@gen_tester
|
||||||
|
VIEW interface
|
||||||
|
GRAPHIC 14,0 51 1
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1182,0 56 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1265,0 57 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 55,0 58 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 702,0 59 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 47,0 60 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 596,0 61 0
|
||||||
|
LIBRARY WaveformGenerator_test
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 64
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 954,0 67 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 421,0 68 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 71
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 73
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 954,0 75 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 961,0 76 1
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 55,0 81 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 702,0 82 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 47,0 83 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 596,0 84 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1182,0 86 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1265,0 88 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 421,0 91 0
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 428,0 92 1
|
||||||
|
DESIGN waveform@gen_tb
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 105
|
||||||
@ -0,0 +1,33 @@
|
|||||||
|
DESIGN waveform@gen_tester
|
||||||
|
VIEW interface
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN waveform@gen_tester
|
||||||
|
VIEW interface
|
||||||
|
GRAPHIC 18,0 8 0
|
||||||
|
DESIGN waveform@gen_tester
|
||||||
|
VIEW interface
|
||||||
|
GRAPHIC 13,0 13 1
|
||||||
|
DESIGN waveform@gen_tester
|
||||||
|
VIEW interface
|
||||||
|
GRAPHIC 904,0 18 0
|
||||||
|
DESIGN waveform@gen_tester
|
||||||
|
VIEW interface
|
||||||
|
GRAPHIC 909,0 19 0
|
||||||
|
DESIGN waveform@gen_tester
|
||||||
|
VIEW interface
|
||||||
|
GRAPHIC 889,0 20 0
|
||||||
|
DESIGN waveform@gen_tester
|
||||||
|
VIEW interface
|
||||||
|
GRAPHIC 894,0 21 0
|
||||||
|
DESIGN waveform@gen_tester
|
||||||
|
VIEW interface
|
||||||
|
GRAPHIC 899,0 22 0
|
||||||
|
DESIGN waveform@gen_tester
|
||||||
|
VIEW interface
|
||||||
|
GRAPHIC 914,0 23 0
|
||||||
|
DESIGN waveform@gen_tester
|
||||||
|
VIEW interface
|
||||||
|
GRAPHIC 1,0 26 0
|
||||||
|
DESIGN waveform@gen_tester
|
||||||
|
VIEW interface
|
||||||
|
GRAPHIC 1,0 27 0
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,6 @@
|
|||||||
|
EDIT_LOCK
|
||||||
|
remi.heredero
|
||||||
|
UNKNOWN
|
||||||
|
WE2330808
|
||||||
|
2208
|
||||||
|
27.02.2024-10:20:27.896000
|
||||||
@ -22,7 +22,7 @@ appVersion "2019.2 (Build 5)"
|
|||||||
model (Symbol
|
model (Symbol
|
||||||
commonDM (CommonDM
|
commonDM (CommonDM
|
||||||
ldm (LogicalDM
|
ldm (LogicalDM
|
||||||
suid 44,0
|
suid 69,0
|
||||||
usingSuid 1
|
usingSuid 1
|
||||||
emptyRow *1 (LEmptyRow
|
emptyRow *1 (LEmptyRow
|
||||||
)
|
)
|
||||||
@ -68,10 +68,10 @@ decl (Decl
|
|||||||
n "clock"
|
n "clock"
|
||||||
t "std_ulogic"
|
t "std_ulogic"
|
||||||
o 1
|
o 1
|
||||||
suid 41,0
|
suid 64,0
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
uid 656,0
|
uid 919,0
|
||||||
)
|
)
|
||||||
*15 (LogPort
|
*15 (LogPort
|
||||||
port (LogicalPort
|
port (LogicalPort
|
||||||
@ -80,10 +80,10 @@ decl (Decl
|
|||||||
n "en"
|
n "en"
|
||||||
t "std_ulogic"
|
t "std_ulogic"
|
||||||
o 2
|
o 2
|
||||||
suid 42,0
|
suid 65,0
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
uid 658,0
|
uid 921,0
|
||||||
)
|
)
|
||||||
*16 (LogPort
|
*16 (LogPort
|
||||||
port (LogicalPort
|
port (LogicalPort
|
||||||
@ -92,23 +92,47 @@ decl (Decl
|
|||||||
n "reset"
|
n "reset"
|
||||||
t "std_ulogic"
|
t "std_ulogic"
|
||||||
o 3
|
o 3
|
||||||
suid 43,0
|
suid 66,0
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
uid 660,0
|
uid 923,0
|
||||||
)
|
)
|
||||||
*17 (LogPort
|
*17 (LogPort
|
||||||
port (LogicalPort
|
port (LogicalPort
|
||||||
|
decl (Decl
|
||||||
|
n "sawtooth"
|
||||||
|
t "unsigned"
|
||||||
|
b "(phaseBitNb-1 DOWNTO 0)"
|
||||||
|
o 5
|
||||||
|
suid 67,0
|
||||||
|
)
|
||||||
|
)
|
||||||
|
uid 925,0
|
||||||
|
)
|
||||||
|
*18 (LogPort
|
||||||
|
port (LogicalPort
|
||||||
|
decl (Decl
|
||||||
|
n "square"
|
||||||
|
t "unsigned"
|
||||||
|
b "(signalBitNb-1 DOWNTO 0)"
|
||||||
|
o 6
|
||||||
|
suid 68,0
|
||||||
|
)
|
||||||
|
)
|
||||||
|
uid 927,0
|
||||||
|
)
|
||||||
|
*19 (LogPort
|
||||||
|
port (LogicalPort
|
||||||
m 1
|
m 1
|
||||||
decl (Decl
|
decl (Decl
|
||||||
n "step"
|
n "step"
|
||||||
t "unsigned"
|
t "unsigned"
|
||||||
b "(bitNb-1 DOWNTO 0)"
|
b "(bitNb-1 DOWNTO 0)"
|
||||||
o 4
|
o 4
|
||||||
suid 44,0
|
suid 69,0
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
uid 662,0
|
uid 929,0
|
||||||
)
|
)
|
||||||
]
|
]
|
||||||
)
|
)
|
||||||
@ -117,7 +141,7 @@ displayShortBounds 1
|
|||||||
editShortBounds 1
|
editShortBounds 1
|
||||||
uid 62,0
|
uid 62,0
|
||||||
optionalChildren [
|
optionalChildren [
|
||||||
*18 (Sheet
|
*20 (Sheet
|
||||||
sheetRow (SheetRow
|
sheetRow (SheetRow
|
||||||
headerVa (MVa
|
headerVa (MVa
|
||||||
cellColor "49152,49152,49152"
|
cellColor "49152,49152,49152"
|
||||||
@ -134,55 +158,67 @@ cellColor "39936,56832,65280"
|
|||||||
fontColor "0,0,0"
|
fontColor "0,0,0"
|
||||||
font "Tahoma,10,0"
|
font "Tahoma,10,0"
|
||||||
)
|
)
|
||||||
emptyMRCItem *19 (MRCItem
|
emptyMRCItem *21 (MRCItem
|
||||||
litem &1
|
litem &1
|
||||||
pos 4
|
pos 4
|
||||||
dimension 20
|
dimension 20
|
||||||
)
|
)
|
||||||
uid 64,0
|
uid 64,0
|
||||||
optionalChildren [
|
optionalChildren [
|
||||||
*20 (MRCItem
|
*22 (MRCItem
|
||||||
litem &2
|
litem &2
|
||||||
pos 0
|
pos 0
|
||||||
dimension 20
|
dimension 20
|
||||||
uid 65,0
|
uid 65,0
|
||||||
)
|
)
|
||||||
*21 (MRCItem
|
*23 (MRCItem
|
||||||
litem &3
|
litem &3
|
||||||
pos 1
|
pos 1
|
||||||
dimension 23
|
dimension 23
|
||||||
uid 66,0
|
uid 66,0
|
||||||
)
|
)
|
||||||
*22 (MRCItem
|
*24 (MRCItem
|
||||||
litem &4
|
litem &4
|
||||||
pos 2
|
pos 2
|
||||||
hidden 1
|
hidden 1
|
||||||
dimension 20
|
dimension 20
|
||||||
uid 67,0
|
uid 67,0
|
||||||
)
|
)
|
||||||
*23 (MRCItem
|
*25 (MRCItem
|
||||||
litem &14
|
litem &14
|
||||||
pos 0
|
pos 0
|
||||||
dimension 20
|
dimension 20
|
||||||
uid 657,0
|
uid 920,0
|
||||||
)
|
)
|
||||||
*24 (MRCItem
|
*26 (MRCItem
|
||||||
litem &15
|
litem &15
|
||||||
pos 1
|
pos 1
|
||||||
dimension 20
|
dimension 20
|
||||||
uid 659,0
|
uid 922,0
|
||||||
)
|
)
|
||||||
*25 (MRCItem
|
*27 (MRCItem
|
||||||
litem &16
|
litem &16
|
||||||
pos 2
|
pos 2
|
||||||
dimension 20
|
dimension 20
|
||||||
uid 661,0
|
uid 924,0
|
||||||
)
|
)
|
||||||
*26 (MRCItem
|
*28 (MRCItem
|
||||||
litem &17
|
litem &17
|
||||||
pos 3
|
pos 3
|
||||||
dimension 20
|
dimension 20
|
||||||
uid 663,0
|
uid 926,0
|
||||||
|
)
|
||||||
|
*29 (MRCItem
|
||||||
|
litem &18
|
||||||
|
pos 4
|
||||||
|
dimension 20
|
||||||
|
uid 928,0
|
||||||
|
)
|
||||||
|
*30 (MRCItem
|
||||||
|
litem &19
|
||||||
|
pos 5
|
||||||
|
dimension 20
|
||||||
|
uid 930,0
|
||||||
)
|
)
|
||||||
]
|
]
|
||||||
)
|
)
|
||||||
@ -195,49 +231,49 @@ textAngle 90
|
|||||||
)
|
)
|
||||||
uid 68,0
|
uid 68,0
|
||||||
optionalChildren [
|
optionalChildren [
|
||||||
*27 (MRCItem
|
*31 (MRCItem
|
||||||
litem &5
|
litem &5
|
||||||
pos 0
|
pos 0
|
||||||
dimension 20
|
dimension 20
|
||||||
uid 69,0
|
uid 69,0
|
||||||
)
|
)
|
||||||
*28 (MRCItem
|
*32 (MRCItem
|
||||||
litem &7
|
litem &7
|
||||||
pos 1
|
pos 1
|
||||||
dimension 50
|
dimension 50
|
||||||
uid 70,0
|
uid 70,0
|
||||||
)
|
)
|
||||||
*29 (MRCItem
|
*33 (MRCItem
|
||||||
litem &8
|
litem &8
|
||||||
pos 2
|
pos 2
|
||||||
dimension 100
|
dimension 100
|
||||||
uid 71,0
|
uid 71,0
|
||||||
)
|
)
|
||||||
*30 (MRCItem
|
*34 (MRCItem
|
||||||
litem &9
|
litem &9
|
||||||
pos 3
|
pos 3
|
||||||
dimension 50
|
dimension 50
|
||||||
uid 72,0
|
uid 72,0
|
||||||
)
|
)
|
||||||
*31 (MRCItem
|
*35 (MRCItem
|
||||||
litem &10
|
litem &10
|
||||||
pos 4
|
pos 4
|
||||||
dimension 100
|
dimension 100
|
||||||
uid 73,0
|
uid 73,0
|
||||||
)
|
)
|
||||||
*32 (MRCItem
|
*36 (MRCItem
|
||||||
litem &11
|
litem &11
|
||||||
pos 5
|
pos 5
|
||||||
dimension 100
|
dimension 100
|
||||||
uid 74,0
|
uid 74,0
|
||||||
)
|
)
|
||||||
*33 (MRCItem
|
*37 (MRCItem
|
||||||
litem &12
|
litem &12
|
||||||
pos 6
|
pos 6
|
||||||
dimension 50
|
dimension 50
|
||||||
uid 75,0
|
uid 75,0
|
||||||
)
|
)
|
||||||
*34 (MRCItem
|
*38 (MRCItem
|
||||||
litem &13
|
litem &13
|
||||||
pos 7
|
pos 7
|
||||||
dimension 80
|
dimension 80
|
||||||
@ -258,41 +294,41 @@ uid 48,0
|
|||||||
)
|
)
|
||||||
genericsCommonDM (CommonDM
|
genericsCommonDM (CommonDM
|
||||||
ldm (LogicalDM
|
ldm (LogicalDM
|
||||||
emptyRow *35 (LEmptyRow
|
emptyRow *39 (LEmptyRow
|
||||||
)
|
)
|
||||||
uid 78,0
|
uid 78,0
|
||||||
optionalChildren [
|
optionalChildren [
|
||||||
*36 (RefLabelRowHdr
|
*40 (RefLabelRowHdr
|
||||||
)
|
)
|
||||||
*37 (TitleRowHdr
|
*41 (TitleRowHdr
|
||||||
)
|
)
|
||||||
*38 (FilterRowHdr
|
*42 (FilterRowHdr
|
||||||
)
|
)
|
||||||
*39 (RefLabelColHdr
|
*43 (RefLabelColHdr
|
||||||
tm "RefLabelColHdrMgr"
|
tm "RefLabelColHdrMgr"
|
||||||
)
|
)
|
||||||
*40 (RowExpandColHdr
|
*44 (RowExpandColHdr
|
||||||
tm "RowExpandColHdrMgr"
|
tm "RowExpandColHdrMgr"
|
||||||
)
|
)
|
||||||
*41 (GroupColHdr
|
*45 (GroupColHdr
|
||||||
tm "GroupColHdrMgr"
|
tm "GroupColHdrMgr"
|
||||||
)
|
)
|
||||||
*42 (NameColHdr
|
*46 (NameColHdr
|
||||||
tm "GenericNameColHdrMgr"
|
tm "GenericNameColHdrMgr"
|
||||||
)
|
)
|
||||||
*43 (TypeColHdr
|
*47 (TypeColHdr
|
||||||
tm "GenericTypeColHdrMgr"
|
tm "GenericTypeColHdrMgr"
|
||||||
)
|
)
|
||||||
*44 (InitColHdr
|
*48 (InitColHdr
|
||||||
tm "GenericValueColHdrMgr"
|
tm "GenericValueColHdrMgr"
|
||||||
)
|
)
|
||||||
*45 (PragmaColHdr
|
*49 (PragmaColHdr
|
||||||
tm "GenericPragmaColHdrMgr"
|
tm "GenericPragmaColHdrMgr"
|
||||||
)
|
)
|
||||||
*46 (EolColHdr
|
*50 (EolColHdr
|
||||||
tm "GenericEolColHdrMgr"
|
tm "GenericEolColHdrMgr"
|
||||||
)
|
)
|
||||||
*47 (LogGeneric
|
*51 (LogGeneric
|
||||||
generic (GiElement
|
generic (GiElement
|
||||||
name "bitNb"
|
name "bitNb"
|
||||||
type "positive"
|
type "positive"
|
||||||
@ -300,7 +336,7 @@ value "16"
|
|||||||
)
|
)
|
||||||
uid 229,0
|
uid 229,0
|
||||||
)
|
)
|
||||||
*48 (LogGeneric
|
*52 (LogGeneric
|
||||||
generic (GiElement
|
generic (GiElement
|
||||||
name "clockFrequency"
|
name "clockFrequency"
|
||||||
type "real"
|
type "real"
|
||||||
@ -315,7 +351,7 @@ displayShortBounds 1
|
|||||||
editShortBounds 1
|
editShortBounds 1
|
||||||
uid 90,0
|
uid 90,0
|
||||||
optionalChildren [
|
optionalChildren [
|
||||||
*49 (Sheet
|
*53 (Sheet
|
||||||
sheetRow (SheetRow
|
sheetRow (SheetRow
|
||||||
headerVa (MVa
|
headerVa (MVa
|
||||||
cellColor "49152,49152,49152"
|
cellColor "49152,49152,49152"
|
||||||
@ -332,40 +368,40 @@ cellColor "39936,56832,65280"
|
|||||||
fontColor "0,0,0"
|
fontColor "0,0,0"
|
||||||
font "Tahoma,10,0"
|
font "Tahoma,10,0"
|
||||||
)
|
)
|
||||||
emptyMRCItem *50 (MRCItem
|
emptyMRCItem *54 (MRCItem
|
||||||
litem &35
|
litem &39
|
||||||
pos 2
|
pos 2
|
||||||
dimension 20
|
dimension 20
|
||||||
)
|
)
|
||||||
uid 92,0
|
uid 92,0
|
||||||
optionalChildren [
|
optionalChildren [
|
||||||
*51 (MRCItem
|
*55 (MRCItem
|
||||||
litem &36
|
litem &40
|
||||||
pos 0
|
pos 0
|
||||||
dimension 20
|
dimension 20
|
||||||
uid 93,0
|
uid 93,0
|
||||||
)
|
)
|
||||||
*52 (MRCItem
|
*56 (MRCItem
|
||||||
litem &37
|
litem &41
|
||||||
pos 1
|
pos 1
|
||||||
dimension 23
|
dimension 23
|
||||||
uid 94,0
|
uid 94,0
|
||||||
)
|
)
|
||||||
*53 (MRCItem
|
*57 (MRCItem
|
||||||
litem &38
|
litem &42
|
||||||
pos 2
|
pos 2
|
||||||
hidden 1
|
hidden 1
|
||||||
dimension 20
|
dimension 20
|
||||||
uid 95,0
|
uid 95,0
|
||||||
)
|
)
|
||||||
*54 (MRCItem
|
*58 (MRCItem
|
||||||
litem &47
|
litem &51
|
||||||
pos 0
|
pos 0
|
||||||
dimension 20
|
dimension 20
|
||||||
uid 230,0
|
uid 230,0
|
||||||
)
|
)
|
||||||
*55 (MRCItem
|
*59 (MRCItem
|
||||||
litem &48
|
litem &52
|
||||||
pos 1
|
pos 1
|
||||||
dimension 20
|
dimension 20
|
||||||
uid 612,0
|
uid 612,0
|
||||||
@ -381,44 +417,44 @@ textAngle 90
|
|||||||
)
|
)
|
||||||
uid 96,0
|
uid 96,0
|
||||||
optionalChildren [
|
optionalChildren [
|
||||||
*56 (MRCItem
|
*60 (MRCItem
|
||||||
litem &39
|
litem &43
|
||||||
pos 0
|
pos 0
|
||||||
dimension 20
|
dimension 20
|
||||||
uid 97,0
|
uid 97,0
|
||||||
)
|
)
|
||||||
*57 (MRCItem
|
*61 (MRCItem
|
||||||
litem &41
|
litem &45
|
||||||
pos 1
|
pos 1
|
||||||
dimension 50
|
dimension 50
|
||||||
uid 98,0
|
uid 98,0
|
||||||
)
|
)
|
||||||
*58 (MRCItem
|
*62 (MRCItem
|
||||||
litem &42
|
litem &46
|
||||||
pos 2
|
pos 2
|
||||||
dimension 100
|
dimension 100
|
||||||
uid 99,0
|
uid 99,0
|
||||||
)
|
)
|
||||||
*59 (MRCItem
|
*63 (MRCItem
|
||||||
litem &43
|
litem &47
|
||||||
pos 3
|
pos 3
|
||||||
dimension 100
|
dimension 100
|
||||||
uid 100,0
|
uid 100,0
|
||||||
)
|
)
|
||||||
*60 (MRCItem
|
*64 (MRCItem
|
||||||
litem &44
|
litem &48
|
||||||
pos 4
|
pos 4
|
||||||
dimension 50
|
dimension 50
|
||||||
uid 101,0
|
uid 101,0
|
||||||
)
|
)
|
||||||
*61 (MRCItem
|
*65 (MRCItem
|
||||||
litem &45
|
litem &49
|
||||||
pos 5
|
pos 5
|
||||||
dimension 50
|
dimension 50
|
||||||
uid 102,0
|
uid 102,0
|
||||||
)
|
)
|
||||||
*62 (MRCItem
|
*66 (MRCItem
|
||||||
litem &46
|
litem &50
|
||||||
pos 6
|
pos 6
|
||||||
dimension 80
|
dimension 80
|
||||||
uid 103,0
|
uid 103,0
|
||||||
@ -445,23 +481,23 @@ value " "
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "HDLDir"
|
variable "HDLDir"
|
||||||
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hdl"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hdl"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "HDSDir"
|
variable "HDSDir"
|
||||||
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "SideDataDesignDir"
|
variable "SideDataDesignDir"
|
||||||
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveform@gen_tester\\interface.info"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveform@gen_tester\\interface.info"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "SideDataUserDir"
|
variable "SideDataUserDir"
|
||||||
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveform@gen_tester\\interface.user"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveform@gen_tester\\interface.user"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "SourceDir"
|
variable "SourceDir"
|
||||||
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "appl"
|
variable "appl"
|
||||||
@ -485,27 +521,27 @@ value "%(unit)_%(view)_config"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "d"
|
variable "d"
|
||||||
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveform@gen_tester"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveform@gen_tester"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "d_logical"
|
variable "d_logical"
|
||||||
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveformGen_tester"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveformGen_tester"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "date"
|
variable "date"
|
||||||
value "28.04.2023"
|
value "27.02.2024"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "day"
|
variable "day"
|
||||||
value "ven."
|
value "mar."
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "day_long"
|
variable "day_long"
|
||||||
value "vendredi"
|
value "mardi"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "dd"
|
variable "dd"
|
||||||
value "28"
|
value "27"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "designName"
|
variable "designName"
|
||||||
@ -533,11 +569,11 @@ value "interface"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_author"
|
variable "graphical_source_author"
|
||||||
value "axel.amand"
|
value "remi.heredero"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_date"
|
variable "graphical_source_date"
|
||||||
value "28.04.2023"
|
value "27.02.2024"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_group"
|
variable "graphical_source_group"
|
||||||
@ -545,11 +581,11 @@ value "UNKNOWN"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_host"
|
variable "graphical_source_host"
|
||||||
value "WE7860"
|
value "WE2330808"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_time"
|
variable "graphical_source_time"
|
||||||
value "14:39:31"
|
value "11:05:34"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "group"
|
variable "group"
|
||||||
@ -557,7 +593,7 @@ value "UNKNOWN"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "host"
|
variable "host"
|
||||||
value "WE7860"
|
value "WE2330808"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "language"
|
variable "language"
|
||||||
@ -573,7 +609,7 @@ value "$SCRATCH_DIR/WaveformGenerator_test"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "mm"
|
variable "mm"
|
||||||
value "04"
|
value "02"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "module_name"
|
variable "module_name"
|
||||||
@ -581,19 +617,19 @@ value "waveformGen_tester"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "month"
|
variable "month"
|
||||||
value "avr."
|
value "févr."
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "month_long"
|
variable "month_long"
|
||||||
value "avril"
|
value "février"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "p"
|
variable "p"
|
||||||
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveform@gen_tester\\interface"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveform@gen_tester\\interface"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "p_logical"
|
variable "p_logical"
|
||||||
value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveformGen_tester\\interface"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveformGen_tester\\interface"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "package_name"
|
variable "package_name"
|
||||||
@ -673,7 +709,7 @@ value "interface"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "time"
|
variable "time"
|
||||||
value "14:39:31"
|
value "11:05:34"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "unit"
|
variable "unit"
|
||||||
@ -681,7 +717,7 @@ value "waveformGen_tester"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "user"
|
variable "user"
|
||||||
value "axel.amand"
|
value "remi.heredero"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "version"
|
variable "version"
|
||||||
@ -693,25 +729,25 @@ value "interface"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "year"
|
variable "year"
|
||||||
value "2023"
|
value "2024"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "yy"
|
variable "yy"
|
||||||
value "23"
|
value "24"
|
||||||
)
|
)
|
||||||
]
|
]
|
||||||
)
|
)
|
||||||
LanguageMgr "Vhdl2008LangMgr"
|
LanguageMgr "Vhdl2008LangMgr"
|
||||||
uid 47,0
|
uid 47,0
|
||||||
optionalChildren [
|
optionalChildren [
|
||||||
*63 (SymbolBody
|
*67 (SymbolBody
|
||||||
uid 8,0
|
uid 8,0
|
||||||
optionalChildren [
|
optionalChildren [
|
||||||
*64 (CptPort
|
*68 (CptPort
|
||||||
uid 636,0
|
uid 889,0
|
||||||
ps "OnEdgeStrategy"
|
ps "OnEdgeStrategy"
|
||||||
shape (Triangle
|
shape (Triangle
|
||||||
uid 637,0
|
uid 890,0
|
||||||
va (VaSet
|
va (VaSet
|
||||||
vasetType 1
|
vasetType 1
|
||||||
fg "0,65535,0"
|
fg "0,65535,0"
|
||||||
@ -719,11 +755,11 @@ fg "0,65535,0"
|
|||||||
xt "28625,5250,29375,6000"
|
xt "28625,5250,29375,6000"
|
||||||
)
|
)
|
||||||
tg (CPTG
|
tg (CPTG
|
||||||
uid 638,0
|
uid 891,0
|
||||||
ps "CptPortTextPlaceStrategy"
|
ps "CptPortTextPlaceStrategy"
|
||||||
stg "RightVerticalLayoutStrategy"
|
stg "RightVerticalLayoutStrategy"
|
||||||
f (Text
|
f (Text
|
||||||
uid 639,0
|
uid 892,0
|
||||||
ro 270
|
ro 270
|
||||||
va (VaSet
|
va (VaSet
|
||||||
font "Verdana,12,0"
|
font "Verdana,12,0"
|
||||||
@ -736,12 +772,12 @@ tm "CptPortNameMgr"
|
|||||||
)
|
)
|
||||||
)
|
)
|
||||||
dt (MLText
|
dt (MLText
|
||||||
uid 640,0
|
uid 893,0
|
||||||
va (VaSet
|
va (VaSet
|
||||||
font "Courier New,8,0"
|
font "Courier New,8,0"
|
||||||
)
|
)
|
||||||
xt "44000,2000,59500,2800"
|
xt "44000,3600,61000,4400"
|
||||||
st "clock : OUT std_ulogic ;
|
st "clock : OUT std_ulogic ;
|
||||||
"
|
"
|
||||||
)
|
)
|
||||||
thePort (LogicalPort
|
thePort (LogicalPort
|
||||||
@ -750,15 +786,15 @@ decl (Decl
|
|||||||
n "clock"
|
n "clock"
|
||||||
t "std_ulogic"
|
t "std_ulogic"
|
||||||
o 1
|
o 1
|
||||||
suid 41,0
|
suid 64,0
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
*65 (CptPort
|
*69 (CptPort
|
||||||
uid 641,0
|
uid 894,0
|
||||||
ps "OnEdgeStrategy"
|
ps "OnEdgeStrategy"
|
||||||
shape (Triangle
|
shape (Triangle
|
||||||
uid 642,0
|
uid 895,0
|
||||||
va (VaSet
|
va (VaSet
|
||||||
vasetType 1
|
vasetType 1
|
||||||
fg "0,65535,0"
|
fg "0,65535,0"
|
||||||
@ -766,11 +802,11 @@ fg "0,65535,0"
|
|||||||
xt "26625,5250,27375,6000"
|
xt "26625,5250,27375,6000"
|
||||||
)
|
)
|
||||||
tg (CPTG
|
tg (CPTG
|
||||||
uid 643,0
|
uid 896,0
|
||||||
ps "CptPortTextPlaceStrategy"
|
ps "CptPortTextPlaceStrategy"
|
||||||
stg "RightVerticalLayoutStrategy"
|
stg "RightVerticalLayoutStrategy"
|
||||||
f (Text
|
f (Text
|
||||||
uid 644,0
|
uid 897,0
|
||||||
ro 270
|
ro 270
|
||||||
va (VaSet
|
va (VaSet
|
||||||
font "Verdana,12,0"
|
font "Verdana,12,0"
|
||||||
@ -783,12 +819,12 @@ tm "CptPortNameMgr"
|
|||||||
)
|
)
|
||||||
)
|
)
|
||||||
dt (MLText
|
dt (MLText
|
||||||
uid 645,0
|
uid 898,0
|
||||||
va (VaSet
|
va (VaSet
|
||||||
font "Courier New,8,0"
|
font "Courier New,8,0"
|
||||||
)
|
)
|
||||||
xt "44000,2800,59500,3600"
|
xt "44000,4400,61000,5200"
|
||||||
st "en : OUT std_ulogic ;
|
st "en : OUT std_ulogic ;
|
||||||
"
|
"
|
||||||
)
|
)
|
||||||
thePort (LogicalPort
|
thePort (LogicalPort
|
||||||
@ -797,15 +833,15 @@ decl (Decl
|
|||||||
n "en"
|
n "en"
|
||||||
t "std_ulogic"
|
t "std_ulogic"
|
||||||
o 2
|
o 2
|
||||||
suid 42,0
|
suid 65,0
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
*66 (CptPort
|
*70 (CptPort
|
||||||
uid 646,0
|
uid 899,0
|
||||||
ps "OnEdgeStrategy"
|
ps "OnEdgeStrategy"
|
||||||
shape (Triangle
|
shape (Triangle
|
||||||
uid 647,0
|
uid 900,0
|
||||||
va (VaSet
|
va (VaSet
|
||||||
vasetType 1
|
vasetType 1
|
||||||
fg "0,65535,0"
|
fg "0,65535,0"
|
||||||
@ -813,11 +849,11 @@ fg "0,65535,0"
|
|||||||
xt "30625,5250,31375,6000"
|
xt "30625,5250,31375,6000"
|
||||||
)
|
)
|
||||||
tg (CPTG
|
tg (CPTG
|
||||||
uid 648,0
|
uid 901,0
|
||||||
ps "CptPortTextPlaceStrategy"
|
ps "CptPortTextPlaceStrategy"
|
||||||
stg "RightVerticalLayoutStrategy"
|
stg "RightVerticalLayoutStrategy"
|
||||||
f (Text
|
f (Text
|
||||||
uid 649,0
|
uid 902,0
|
||||||
ro 270
|
ro 270
|
||||||
va (VaSet
|
va (VaSet
|
||||||
font "Verdana,12,0"
|
font "Verdana,12,0"
|
||||||
@ -830,12 +866,12 @@ tm "CptPortNameMgr"
|
|||||||
)
|
)
|
||||||
)
|
)
|
||||||
dt (MLText
|
dt (MLText
|
||||||
uid 650,0
|
uid 903,0
|
||||||
va (VaSet
|
va (VaSet
|
||||||
font "Courier New,8,0"
|
font "Courier New,8,0"
|
||||||
)
|
)
|
||||||
xt "44000,3600,59500,4400"
|
xt "44000,5200,61000,6000"
|
||||||
st "reset : OUT std_ulogic ;
|
st "reset : OUT std_ulogic ;
|
||||||
"
|
"
|
||||||
)
|
)
|
||||||
thePort (LogicalPort
|
thePort (LogicalPort
|
||||||
@ -844,15 +880,111 @@ decl (Decl
|
|||||||
n "reset"
|
n "reset"
|
||||||
t "std_ulogic"
|
t "std_ulogic"
|
||||||
o 3
|
o 3
|
||||||
suid 43,0
|
suid 66,0
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
*67 (CptPort
|
*71 (CptPort
|
||||||
uid 651,0
|
uid 904,0
|
||||||
ps "OnEdgeStrategy"
|
ps "OnEdgeStrategy"
|
||||||
shape (Triangle
|
shape (Triangle
|
||||||
uid 652,0
|
uid 905,0
|
||||||
|
ro 180
|
||||||
|
va (VaSet
|
||||||
|
vasetType 1
|
||||||
|
fg "0,65535,0"
|
||||||
|
)
|
||||||
|
xt "63625,5250,64375,6000"
|
||||||
|
)
|
||||||
|
tg (CPTG
|
||||||
|
uid 906,0
|
||||||
|
ps "CptPortTextPlaceStrategy"
|
||||||
|
stg "RightVerticalLayoutStrategy"
|
||||||
|
f (Text
|
||||||
|
uid 907,0
|
||||||
|
ro 270
|
||||||
|
va (VaSet
|
||||||
|
font "Verdana,12,0"
|
||||||
|
)
|
||||||
|
xt "63300,7000,64700,13800"
|
||||||
|
st "sawtooth"
|
||||||
|
ju 2
|
||||||
|
blo "64500,7000"
|
||||||
|
tm "CptPortNameMgr"
|
||||||
|
)
|
||||||
|
)
|
||||||
|
dt (MLText
|
||||||
|
uid 908,0
|
||||||
|
va (VaSet
|
||||||
|
font "Courier New,8,0"
|
||||||
|
)
|
||||||
|
xt "44000,2000,72000,2800"
|
||||||
|
st "sawtooth : IN unsigned (phaseBitNb-1 DOWNTO 0) ;
|
||||||
|
"
|
||||||
|
)
|
||||||
|
thePort (LogicalPort
|
||||||
|
decl (Decl
|
||||||
|
n "sawtooth"
|
||||||
|
t "unsigned"
|
||||||
|
b "(phaseBitNb-1 DOWNTO 0)"
|
||||||
|
o 5
|
||||||
|
suid 67,0
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
*72 (CptPort
|
||||||
|
uid 909,0
|
||||||
|
ps "OnEdgeStrategy"
|
||||||
|
shape (Triangle
|
||||||
|
uid 910,0
|
||||||
|
ro 180
|
||||||
|
va (VaSet
|
||||||
|
vasetType 1
|
||||||
|
fg "0,65535,0"
|
||||||
|
)
|
||||||
|
xt "60625,5250,61375,6000"
|
||||||
|
)
|
||||||
|
tg (CPTG
|
||||||
|
uid 911,0
|
||||||
|
ps "CptPortTextPlaceStrategy"
|
||||||
|
stg "RightVerticalLayoutStrategy"
|
||||||
|
f (Text
|
||||||
|
uid 912,0
|
||||||
|
ro 270
|
||||||
|
va (VaSet
|
||||||
|
font "Verdana,12,0"
|
||||||
|
)
|
||||||
|
xt "60300,7000,61700,12200"
|
||||||
|
st "square"
|
||||||
|
ju 2
|
||||||
|
blo "61500,7000"
|
||||||
|
tm "CptPortNameMgr"
|
||||||
|
)
|
||||||
|
)
|
||||||
|
dt (MLText
|
||||||
|
uid 913,0
|
||||||
|
va (VaSet
|
||||||
|
font "Courier New,8,0"
|
||||||
|
)
|
||||||
|
xt "44000,2800,72500,3600"
|
||||||
|
st "square : IN unsigned (signalBitNb-1 DOWNTO 0) ;
|
||||||
|
"
|
||||||
|
)
|
||||||
|
thePort (LogicalPort
|
||||||
|
decl (Decl
|
||||||
|
n "square"
|
||||||
|
t "unsigned"
|
||||||
|
b "(signalBitNb-1 DOWNTO 0)"
|
||||||
|
o 6
|
||||||
|
suid 68,0
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
*73 (CptPort
|
||||||
|
uid 914,0
|
||||||
|
ps "OnEdgeStrategy"
|
||||||
|
shape (Triangle
|
||||||
|
uid 915,0
|
||||||
va (VaSet
|
va (VaSet
|
||||||
vasetType 1
|
vasetType 1
|
||||||
fg "0,65535,0"
|
fg "0,65535,0"
|
||||||
@ -860,11 +992,11 @@ fg "0,65535,0"
|
|||||||
xt "22625,5250,23375,6000"
|
xt "22625,5250,23375,6000"
|
||||||
)
|
)
|
||||||
tg (CPTG
|
tg (CPTG
|
||||||
uid 653,0
|
uid 916,0
|
||||||
ps "CptPortTextPlaceStrategy"
|
ps "CptPortTextPlaceStrategy"
|
||||||
stg "RightVerticalLayoutStrategy"
|
stg "RightVerticalLayoutStrategy"
|
||||||
f (Text
|
f (Text
|
||||||
uid 654,0
|
uid 917,0
|
||||||
ro 270
|
ro 270
|
||||||
va (VaSet
|
va (VaSet
|
||||||
font "Verdana,12,0"
|
font "Verdana,12,0"
|
||||||
@ -877,12 +1009,12 @@ tm "CptPortNameMgr"
|
|||||||
)
|
)
|
||||||
)
|
)
|
||||||
dt (MLText
|
dt (MLText
|
||||||
uid 655,0
|
uid 918,0
|
||||||
va (VaSet
|
va (VaSet
|
||||||
font "Courier New,8,0"
|
font "Courier New,8,0"
|
||||||
)
|
)
|
||||||
xt "44000,4400,67000,5200"
|
xt "44000,6000,68500,6800"
|
||||||
st "step : OUT unsigned (bitNb-1 DOWNTO 0)
|
st "step : OUT unsigned (bitNb-1 DOWNTO 0)
|
||||||
"
|
"
|
||||||
)
|
)
|
||||||
thePort (LogicalPort
|
thePort (LogicalPort
|
||||||
@ -892,7 +1024,7 @@ n "step"
|
|||||||
t "unsigned"
|
t "unsigned"
|
||||||
b "(bitNb-1 DOWNTO 0)"
|
b "(bitNb-1 DOWNTO 0)"
|
||||||
o 4
|
o 4
|
||||||
suid 44,0
|
suid 69,0
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
@ -930,7 +1062,7 @@ st "waveformGen_tester"
|
|||||||
blo "35650,10800"
|
blo "35650,10800"
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
gi *68 (GenericInterface
|
gi *74 (GenericInterface
|
||||||
uid 13,0
|
uid 13,0
|
||||||
ps "CenterOffsetStrategy"
|
ps "CenterOffsetStrategy"
|
||||||
matrix (Matrix
|
matrix (Matrix
|
||||||
@ -984,11 +1116,11 @@ xShown 1
|
|||||||
yShown 1
|
yShown 1
|
||||||
color "26368,26368,26368"
|
color "26368,26368,26368"
|
||||||
)
|
)
|
||||||
packageList *69 (PackageList
|
packageList *75 (PackageList
|
||||||
uid 16,0
|
uid 16,0
|
||||||
stg "VerticalLayoutStrategy"
|
stg "VerticalLayoutStrategy"
|
||||||
textVec [
|
textVec [
|
||||||
*70 (Text
|
*76 (Text
|
||||||
uid 17,0
|
uid 17,0
|
||||||
va (VaSet
|
va (VaSet
|
||||||
font "arial,8,1"
|
font "arial,8,1"
|
||||||
@ -997,7 +1129,7 @@ xt "0,0,5400,1000"
|
|||||||
st "Package List"
|
st "Package List"
|
||||||
blo "0,800"
|
blo "0,800"
|
||||||
)
|
)
|
||||||
*71 (MLText
|
*77 (MLText
|
||||||
uid 18,0
|
uid 18,0
|
||||||
va (VaSet
|
va (VaSet
|
||||||
)
|
)
|
||||||
@ -1124,7 +1256,7 @@ st "<cell>"
|
|||||||
blo "22200,16800"
|
blo "22200,16800"
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
gi *72 (GenericInterface
|
gi *78 (GenericInterface
|
||||||
ps "CenterOffsetStrategy"
|
ps "CenterOffsetStrategy"
|
||||||
matrix (Matrix
|
matrix (Matrix
|
||||||
text (MLText
|
text (MLText
|
||||||
@ -1225,7 +1357,7 @@ o 0
|
|||||||
)
|
)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
DeclarativeBlock *73 (SymDeclBlock
|
DeclarativeBlock *79 (SymDeclBlock
|
||||||
uid 1,0
|
uid 1,0
|
||||||
stg "SymDeclLayoutStrategy"
|
stg "SymDeclLayoutStrategy"
|
||||||
declLabel (Text
|
declLabel (Text
|
||||||
@ -1251,9 +1383,9 @@ uid 4,0
|
|||||||
va (VaSet
|
va (VaSet
|
||||||
font "Arial,8,1"
|
font "Arial,8,1"
|
||||||
)
|
)
|
||||||
xt "42000,5200,44400,6200"
|
xt "42000,6800,44400,7800"
|
||||||
st "User:"
|
st "User:"
|
||||||
blo "42000,6000"
|
blo "42000,7600"
|
||||||
)
|
)
|
||||||
internalLabel (Text
|
internalLabel (Text
|
||||||
uid 6,0
|
uid 6,0
|
||||||
@ -1270,7 +1402,7 @@ uid 5,0
|
|||||||
va (VaSet
|
va (VaSet
|
||||||
font "Courier New,8,0"
|
font "Courier New,8,0"
|
||||||
)
|
)
|
||||||
xt "44000,6200,44000,6200"
|
xt "44000,7800,44000,7800"
|
||||||
tm "SyDeclarativeTextMgr"
|
tm "SyDeclarativeTextMgr"
|
||||||
)
|
)
|
||||||
internalText (MLText
|
internalText (MLText
|
||||||
@ -1283,6 +1415,6 @@ xt "42000,0,42000,0"
|
|||||||
tm "SyDeclarativeTextMgr"
|
tm "SyDeclarativeTextMgr"
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
lastUid 663,0
|
lastUid 930,0
|
||||||
activeModelName "Symbol:GEN"
|
activeModelName "Symbol:GEN"
|
||||||
)
|
)
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user