add shift + buffer

02-SplineInterpolator/Prefs/hds.hdp

@@ -1,11 +1,10 @@
-[Concat]
 [ModelSim]
 SplineInterpolator = $SCRATCH_DIR/SplineInterpolator
 SplineInterpolator_test = $SCRATCH_DIR/SplineInterpolator_test
 WaveformGenerator = $SCRATCH_DIR/WaveformGenerator
 WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test
 [hdl]
-ieee = $HDS_HOME/hdl_libs/ieee/hdl
+ieee = $HDS_HOME\hdl_libs\ieee\hdl
 SplineInterpolator = $HDS_PROJECT_DIR/../SplineInterpolator/hdl
 SplineInterpolator_test = $HDS_PROJECT_DIR/../SplineInterpolator_test/hdl
 std = $HDS_HOME/hdl_libs/std/hdl

02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs

@@ -1280,6 +1280,7 @@ projectPaths [
 "C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
 "C:\\work\\edu\\sem\\labo\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
 "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
+"C:\\Users\\uadmin\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
 "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
 ]
 libMappingsRootDir ""
@@ -4149,7 +4150,7 @@ hdsWorkspaceLocation ""
 relativeLibraryRootDir ""
 vmLabelLatestDontAskAgain 0
 vmLabelWorkspaceDontAskAgain 0
-logWindowGeometry "600x573+405+95"
+logWindowGeometry "600x573+406+95"
 diagramBrowserTabNo 0
 showInsertPortHint 0
 showContentFirstTime 0
@@ -6217,9 +6218,9 @@ size 180
 ]
 displayHierarchy 0
 xPos 0
-yPos 14
-width 1936
-height 1056
+yPos 4
+width 892
+height 982
 activeSidePanelTab 2
 activeLibraryTab 2
 sidePanelSize 278

02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs.bak

@@ -1281,6 +1281,7 @@ projectPaths [
 "C:\\work\\edu\\sem\\labo\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
 "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
 "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
+"C:\\Users\\uadmin\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
 ]
 libMappingsRootDir ""
 teamLibMappingsRootDir ""
@@ -4149,7 +4150,7 @@ hdsWorkspaceLocation ""
 relativeLibraryRootDir ""
 vmLabelLatestDontAskAgain 0
 vmLabelWorkspaceDontAskAgain 0
-logWindowGeometry "600x573+405+95"
+logWindowGeometry "600x573+406+95"
 diagramBrowserTabNo 0
 showInsertPortHint 0
 showContentFirstTime 0
@@ -6217,9 +6218,9 @@ size 180
 ]
 displayHierarchy 0
 xPos 0
-yPos 14
-width 1936
-height 1056
+yPos 4
+width 892
+height 982
 activeSidePanelTab 2
 activeLibraryTab 2
 sidePanelSize 278

02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCalculatePolynom_studentVersion.vhd

@@ -1,4 +1,64 @@
 ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS
+
+subtype sample_type is signed(coeffBitNb-1+oversamplingBitNb+10 DOWNTO 0);
+type order0 is array (0 to 0) of sample_type;
+type order1 is array (0 to 1) of sample_type;
+type order2 is array (0 to 2) of sample_type;
+type order3 is array (0 to 3) of sample_type;
+signal cA: order3;
+signal cB: order2;
+signal cC: order1;
+signal cD: order0;
+signal bufferSine: sample_type;
+
 BEGIN
-  sampleOut <= (others => '0');
+
+  process(clock, reset) begin
+    if reset = '1' then
+      cA <= (others => (others => '0'));
+      cB <= (others => (others => '0'));
+      cC <= (others => (others => '0'));
+      cD <= (others => (others => '0'));
+      bufferSine <= (others => '0');
+    elsif rising_edge(clock) then
+
+      if restartPolynom = '1' then
+        cA(3) <= (others => '0');
+        cA(2) <= (others => '0');
+        cA(1) <= (others => '0');
+        cA(0) <= resize(a,sample_type'high+1);
+        
+        cB(2) <= (others => '0');
+        cB(1) <= (others => '0');
+        cB(0) <= resize(b,sample_type'high+1);
+        
+        cC(1) <= (others => '0');
+        cC(0) <= resize(c,sample_type'high+1);
+
+        cD(0) <= resize(d,sample_type'high+1);
+        
+      else
+
+        cC(1) <= cC(0) + cC(1);
+
+        cB(2) <= cB(2) + resize(2*cB(1),sample_type'high+1) + cB(0);
+        cB(1) <= resize(b,sample_type'high+1) + cB(1);
+
+        cA(3) <= cA(3) + resize(3*cA(2),sample_type'high+1) + resize(3*cA(1),sample_type'high+1) + cA(0);
+        cA(2) <= cA(2) + resize(2*cA(1),sample_type'high+1) + cA(0);
+        cA(1) <= resize(A,sample_type'high+1) + cA(1);
+
+      end if;
+
+      bufferSine <= bufferSine + shift_right(cA(3)+cB(2)+cC(1)+cD(0),0);
+
+    end if;
+  end process;
+
+  process(cA, cB, cC, cD) begin
+    --bufferSine <= bufferSine + cA(3)+cB(2)+cC(1)+cD(0);
+  end process;
+
+  --sampleOut <= resize(shift_right(cA(3)+cB(2)+cC(1)+cD(0),oversamplingBitNb),signalBitNb);
+  sampleOut <= resize(bufferSine,signalBitNb);
 END ARCHITECTURE studentVersion;

02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd

@@ -1,7 +1,27 @@
 ARCHITECTURE studentVersion OF interpolatorCoefficients IS
+
+subtype sample is signed(bitNb-1 DOWNTO 0);
+subtype coeff is signed(coeffBitNb-1 DOWNTO 0);
+
+type samples_type is array (1 to 4) of coeff;
+signal samples: samples_type;
+
 BEGIN
-  a <= (others => '0');
-  b <= (others => '0');
-  c <= (others => '0');
-  d <= (others => '0');
+-- a = - sample1 +3·sample2 -3·sample3 + sample4
+-- b = 2·sample1 -5·sample2 +4·sample3 - sample4
+-- c = - sample1 + sample3
+-- d = sample2
+
+  process(sample1, sample2, sample3, sample4) begin
+    samples(1) <= resize(sample1, coeff'high+1);
+    samples(2) <= resize(sample2, coeff'high+1);
+    samples(3) <= resize(sample3, coeff'high+1);
+    samples(4) <= resize(sample4, coeff'high+1);
+  end process;
+
+
+  a <= samples(4) - samples(1) + resize( 3*(samples(2) - samples(3)), coeff'high+1);
+  b <= resize(2*samples(1), coeff'high+1) - resize(5*samples(2), coeff'high+1) + resize(4*samples(3), coeff'high+1) - samples(4);
+  c <= samples(3) - samples(1);
+  d <= samples(2);
 END ARCHITECTURE studentVersion;

02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd

@@ -1,7 +1,28 @@
 ARCHITECTURE studentVersion OF interpolatorShiftRegister IS
+
+subtype sample_type is signed(sampleIn'range);
+type samples_type is array (1 to 4) of sample_type;
+signal samples: samples_type;
+
 BEGIN
-  sample1 <= (others => '0');
-  sample2 <= (others => '0');
-  sample3 <= (others => '0');
-  sample4 <= (others => '0');
+
+  process(clock, reset) begin
+    if reset = '1' then
+      samples <= (others => (others => '0'));
+    elsif rising_edge(clock) then
+
+      if shiftSamples then
+        for i in samples_type'low to samples_type'high-1 loop
+          samples(i+1) <= samples(i);
+        end loop;
+        samples(1) <= sampleIn;
+      end if;
+
+    end if;
+  end process;
+
+  sample1 <= samples(4);
+  sample2 <= samples(3);
+  sample3 <= samples(2);
+  sample4 <= samples(1);
 END ARCHITECTURE studentVersion;

02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd

@@ -1,4 +1,29 @@
 ARCHITECTURE studentVersion OF interpolatorTrigger IS
+
+  signal counter : unsigned(counterBitNb-1 downto 0);
+
 BEGIN
-  triggerOut <= '0';
+
+  process(clock, reset)
+  begin
+    if reset = '1' then
+      counter <= (others => '0');
+    elsif rising_edge(clock) then
+
+      if en = '1' then
+        counter <= counter - 1;
+      end if;
+
+    end if;
+  end process;
+
+  process(counter)
+  begin
+    if counter = 0 then
+      triggerOut <= '1';
+    else
+      triggerOut <= '0';
+    end if;
+  end process;
+
 END ARCHITECTURE studentVersion;

02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd

@@ -8,7 +8,7 @@ BEGIN
 
   phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
 
-  sequenceTable: process(phase)
+  sequenceTable: process(phaseTableAddress)
   begin
     if phase(phase'high-1) = '1' then
       phaseTableAddress2 <= 8 - phaseTableAddress;
@@ -30,9 +30,14 @@ BEGIN
       when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length);
       when others => quarterSine <= (others => '-');
     end case;
+    if phaseTableAddress2 = 0 then
+      if phase(phase'high-1) = '1' then
+        quarterSine <= to_signed(16#7FFF#, quarterSine'length);
+      end if;
+    end if;
   end process quarterTable;
 
-  invert: process(quarterSine)
+  invert: process(quarterSine, phase(phase'high))
   begin
     if phase(phase'high) = '1' then
       sine <= NOT quarterSine;
@@ -41,6 +46,4 @@ BEGIN
     end if;
   end process invert;
 
-  --sine <= quarterSine;
-
 END ARCHITECTURE studentVersion;