fix coeff calculation

02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs

@@ -1281,6 +1281,7 @@ projectPaths [
 "C:\\work\\edu\\sem\\labo\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
 "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
 "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
+"C:\\Users\\uadmin\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
 ]
 libMappingsRootDir ""
 teamLibMappingsRootDir ""
@@ -4149,7 +4150,7 @@ hdsWorkspaceLocation ""
 relativeLibraryRootDir ""
 vmLabelLatestDontAskAgain 0
 vmLabelWorkspaceDontAskAgain 0
-logWindowGeometry "600x573+405+95"
+logWindowGeometry "600x573+406+95"
 diagramBrowserTabNo 0
 showInsertPortHint 0
 showContentFirstTime 0
@@ -6217,9 +6218,9 @@ size 180
 ]
 displayHierarchy 0
 xPos 0
-yPos 14
-width 1936
-height 1056
+yPos 4
+width 892
+height 982
 activeSidePanelTab 2
 activeLibraryTab 2
 sidePanelSize 278

02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCalculatePolynom_studentVersion.vhd

@@ -1,4 +1,20 @@
 ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS
+
+subtype sample_type is signed(sampleIn'range);
+type samples_type is array (1 to 4) of sample_type;
+signal samples: samples_type;
+
 BEGIN
+
+  process(clock, reset) begin
+    if reset = '1' then
+      samples <= (others => (others => '0'));
+    elsif rising_edge(clock) then
+
+
+
+    end if;
+  end process;
+
   sampleOut <= (others => '0');
 END ARCHITECTURE studentVersion;

02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd

@@ -10,18 +10,18 @@ BEGIN
 -- a = - sample1 +3·sample2 -3·sample3 + sample4
 -- b = 2·sample1 -5·sample2 +4·sample3 - sample4
 -- c = - sample1 + sample3
--- d = sample2 
+-- d = sample2
 
   process(sample1, sample2, sample3, sample4) begin
-    samples(4) <= resize(sample1, coeff'high+1);
-    samples(3) <= resize(sample2, coeff'high+1);
-    samples(2) <= resize(sample3, coeff'high+1);
-    samples(1) <= resize(sample4, coeff'high+1);
+    samples(1) <= resize(sample1, coeff'high+1);
+    samples(2) <= resize(sample2, coeff'high+1);
+    samples(3) <= resize(sample3, coeff'high+1);
+    samples(4) <= resize(sample4, coeff'high+1);
   end process;
 
 
   a <= samples(4) - samples(1) + resize( 3*(samples(2) - samples(3)), coeff'high+1);
   b <= resize(2*samples(1), coeff'high+1) - resize(5*samples(2), coeff'high+1) + resize(4*samples(3), coeff'high+1) - samples(4);
   c <= samples(3) - samples(1);
-  d <= samples(4);
+  d <= samples(2);
 END ARCHITECTURE studentVersion;

02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd

@@ -10,17 +10,19 @@ BEGIN
     if reset = '1' then
       samples <= (others => (others => '0'));
     elsif rising_edge(clock) then
+
       if shiftSamples then
         for i in samples_type'low to samples_type'high-1 loop
           samples(i+1) <= samples(i);
         end loop;
         samples(1) <= sampleIn;
       end if;
+
     end if;
   end process;
 
-  sample1 <= samples(1);
-  sample2 <= samples(2);
-  sample3 <= samples(3);
-  sample4 <= samples(4);
+  sample1 <= samples(4);
+  sample2 <= samples(3);
+  sample3 <= samples(2);
+  sample4 <= samples(1);
 END ARCHITECTURE studentVersion;

02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd

@@ -7,11 +7,13 @@ BEGIN
   process(clock, reset)
   begin
     if reset = '1' then
-      counter <= (others => '1');
+      counter <= (others => '0');
     elsif rising_edge(clock) then
+
       if en = '1' then
         counter <= counter - 1;
       end if;
+
     end if;
   end process;
 
@@ -23,5 +25,5 @@ BEGIN
       triggerOut <= '0';
     end if;
   end process;
-        
+
 END ARCHITECTURE studentVersion;