29 lines
686 B
VHDL
29 lines
686 B
VHDL
ARCHITECTURE studentVersion OF interpolatorShiftRegister IS
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subtype sample_type is signed(sampleIn'range);
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type samples_type is array (1 to 4) of sample_type;
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signal samples: samples_type;
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BEGIN
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process(clock, reset) begin
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if reset = '1' then
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samples <= (others => (others => '0'));
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elsif rising_edge(clock) then
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if shiftSamples then
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for i in samples_type'low to samples_type'high-1 loop
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samples(i+1) <= samples(i);
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end loop;
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samples(1) <= sampleIn;
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end if;
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end if;
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end process;
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sample1 <= samples(4);
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sample2 <= samples(3);
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sample3 <= samples(2);
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sample4 <= samples(1);
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END ARCHITECTURE studentVersion;
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