336 lines
22 KiB
Markdown
336 lines
22 KiB
Markdown
[](https://github.com/stnolting/neorv32)
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# The NEORV32 RISC-V Processor
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://stnolting.github.io/neorv32)
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://stnolting.github.io/neorv32/ug)
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[](https://stnolting.github.io/neorv32/sw/files.html)
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[](https://gitter.im/neorv32/community?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
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1. [Overview](#1-Overview)
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* [Key Features](#Project-Key-Features)
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* [Status](#status)
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2. [Processor/SoC Features](#2-NEORV32-Processor-Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results---Processor)
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3. [CPU Features](#3-NEORV32-CPU-Features)
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* [Available ISA Extensions](#Available-ISA-Extensions)
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* [FPGA Implementation Results](#FPGA-Implementation-Results---CPU)
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* [Performance](#Performance)
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4. [Software Framework & Tooling](#4-Software-Framework-and-Tooling)
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5. [**Getting Started**](#5-Getting-Started) :rocket:
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## 1. Overview
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The NEORV32 Processor is a **customizable microcontroller-like system on chip (SoC)** that is based on the RISC-V NEORV32 CPU.
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The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
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custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz.
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Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
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Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
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are executed. Whenever an unexpected situation occurs the application code is informed via precise and resumable hardware exceptions.
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:thinking: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
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:books: For detailed information take a look at the [NEORV32 documentation](https://stnolting.github.io/neorv32/) (online at GitHub-pages).
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:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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To see the changes between _official releases_ visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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:package: [Exemplary setups](https://github.com/stnolting/neorv32/tree/master/setups) targeting
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various FPGA boards and toolchains to get you started.
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:kite: Supported by upstream [Zephyr OS](https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html) and FreeRTOS.
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
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[new discussion](https://github.com/stnolting/neorv32/discussions) if you have questions, comments, ideas or if something is
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not working as expected. Or have a chat on our [gitter channel](https://gitter.im/neorv32/community).
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See how to [contribute](https://github.com/stnolting/neorv32/blob/master/CONTRIBUTING.md).
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:rocket: Check out the [quick links below](#5-Getting-Started) or directly jump to the
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[*User Guide*](https://stnolting.github.io/neorv32/ug/) to get started
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setting up your NEORV32 setup!
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### Project Key Features
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- [x] all-in-one package: [CPU](#3-NEORV32-CPU-Features) plus [SoC](#2-NEORV32-Processor-Features) plus [Software Framework & Tooling](#4-Software-Framework-and-Tooling)
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- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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- [x] be as small as possible while being as RISC-V-compliant as possible
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- [x] from zero to *printf("hello world!");* - completely open source and documented
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- [x] easy to use even for FPGA/RISC-V starters – intended to work *out of the box*
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### Status
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[](https://github.com/stnolting/neorv32/releases)
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[](https://stnolting.github.io/neorv32)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
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\
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AImplementation)
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[](https://github.com/stnolting/neorv32/actions?query=workflow%3AWindows)
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## 2. NEORV32 Processor Features
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The NEORV32 Processor (top entity: [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd))
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provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics
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to allow a flexible customization according to your needs. Note that all modules listed below are _optional_.
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**Memory**
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* processor-internal data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) /
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[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) &
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cache ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache))
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* bootloader ([BOOTLDROM](https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom)) with serial user interface
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* allows booting application code via UART or from external SPI flash
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**Timers**
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* machine system timer, 64-bit ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V spec. compatible
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* general purpose 32-bit timer ([GPTMR](https://stnolting.github.io/neorv32/#_general_purpose_timer_gptmr))
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* watchdog timer ([WDT](https://stnolting.github.io/neorv32/#_watchdog_timer_wdt))
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**Input/Output**
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* standard serial interfaces
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([UART](https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0),
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[SPI](https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi),
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[TWI / I²C](https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi))
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* general purpose [GPIO](https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio) and
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[PWM](https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm)
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* smart LED interface ([NEOLED](https://stnolting.github.io/neorv32/#_smart_led_interface_neoled)) to directly drive _NeoPixel(TM)_ LEDs
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**SoC Connectivity**
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* 32-bit external bus interface, Wishbone b4 compatible
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([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
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* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite master interface
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* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd) for Avalon-MM master interface
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* 32-bit stream link interface with up to 8 independent RX and TX links
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([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
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* AXI4-Stream compatible
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* external interrupt controller with up to 32 channels
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([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
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* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
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for tightly-coupled custom co-processor extensions
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**Advanced**
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* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
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* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via JTAG interface - implementing
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the [*Minimal RISC-V Debug Specification Version 0.13.2*](https://github.com/riscv/riscv-debug-spec)
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and compatible with *OpenOCD* and *gdb*
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* bus keeper to monitor the CPU's bus transactions ([BUSKEEPER](https://stnolting.github.io/neorv32/#_internal_bus_monitor_buskeeper))
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### FPGA Implementation Results - Processor
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The hardware resources used by a specific processor setup is defined by the implemented CPU extensions,
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the configuration of the peripheral modules and some "glue logic".
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Section [_FPGA Implementation Results - Processor Modules_](https://stnolting.github.io/neorv32/#_processor_modules)
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of the online datasheet shows the resource utilization of each optional processor module to allow an
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estimation of the actual setup's hardware requirements.
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The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary FPGA
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setups targeting various FPGA boards and toolchains. These setups also provide resource utilization reports for different
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SoC configurations. The latest utilization reports for those setups can be found in the report of the
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[Implementation Workflow](https://github.com/stnolting/neorv32/actions/workflows/Implementation.yml).
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## 3. NEORV32 CPU Features
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The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd))
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implements the RISC-V 32-bit `rv32` ISA with optional extensions (see below). It is compatible to subsets of the
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*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
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and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
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Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
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(see [`sim/README`](sim/README.md)).
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The core is a little-endian Von-Neumann machine implemented as multi-cycle architecture.
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However, the CPU's _front end_ (instruction fetch) and _back end_ (instruction execution) can work independently to increase performance.
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Currently, three privilege levels (`machine` and optional `user` and `debug_mode`) are supported. The CPU implements all three standard RISC-V machine
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interrupts (`MTI`, `MEI`, `MSI`) plus 16 _fast interrupt requests_ as custom extensions.
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It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
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instruction, breakpoint, environment calls).
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:books: In-depth detailed information regarding the CPU can be found in the
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[_Data Sheet: NEORV32 Central Processing Unit_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
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### Available ISA Extensions
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Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
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documentation section). Note that the `X` extension is always enabled.
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**RV32
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[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/
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[`E`](https://stnolting.github.io/neorv32/#_e_embedded_cpu)]
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[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)]
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[[`B`](https://stnolting.github.io/neorv32/#_b_bit_manipulation_operations)]
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[[`C`](https://stnolting.github.io/neorv32/#_c_compressed_instructions)]
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[[`M`](https://stnolting.github.io/neorv32/#_m_integer_multiplication_and_division)]
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[[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)]
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[[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)]
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[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)]
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[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)]
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[[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_cpu_base_counters)]
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[[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_hardware_performance_monitors)]
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[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
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[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
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[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
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[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]**
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:warning: The `B`, `Zfinx` and `Zmmul` RISC-V extensions are frozen but not officially ratified yet. Hence, there is no
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upstream gcc support. To circumvent this, the NEORV32 software framework provides _intrinsic libraries_ for these extensions.
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### FPGA Implementation Results - CPU
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Implementation results for _exemplary_ CPU configuration generated for an **Intel Cyclone IV EP4CE22F17C6N FPGA**
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using **Intel Quartus Prime Lite 20.1** ("balanced implementation, Slow 1200mV 0C Model").
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| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)) | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
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|:------------------------|:----:|:----:|:----:|:-:|:-------:|
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| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
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| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz |
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| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
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:information_source: An incremental list of CPU extension's hardware utilization can found in the
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[_Data Sheet: FPGA Implementation Results - CPU_](https://stnolting.github.io/neorv32/#_cpu).
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:information_source: The CPU and SoC provide advanced options to optimize for performance, area or energy.
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See [_User Guide: Application-Specific Processor Configuration_](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration)
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for more information.
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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### Performance
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The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute).
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The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
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available CPU extensions.
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The following table shows the performance results (scores and average CPI) for _exemplary_ CPU configurations executing
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2000 iterations of the [CoreMark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) CPU benchmark.
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| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)) | CoreMark Score | CoreMarks/MHz | Average CPI |
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|:------------------------------------------------|:-----:|:----------:|:--------:|
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| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04** |
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| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** |
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| _performance_ (`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54** |
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:information_source: More information regarding the CPU performance can be found in the
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[_Data Sheet: CPU Performance_](https://stnolting.github.io/neorv32/#_cpu_performance).
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## 4. Software Framework and Tooling
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* [core libraries](https://github.com/stnolting/neorv32/tree/master/sw/lib) for high-level usage of the provided functions and peripherals
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* application compilation based on GNU makefiles
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* gcc-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
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* [SVD file](https://github.com/stnolting/neorv32/tree/master/sw/svd) for advanced debugging and IDE integration
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* bootloader with UART interface console
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* runtime environment for handling traps
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* several [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) to get started including CoreMark, FreeRTOS and Conway's Game of Life
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* doxygen-based documentation, available on [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html)
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* supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future: "Verilog-to-Routing") - both, software and hardware can be
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developed and debugged with open source tooling
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* [continuous integration](https://github.com/stnolting/neorv32/actions) is available for:
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* allowing users to see the expected execution/output of the tools
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* ensuring specification compliance
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* catching regressions
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* providing ready-to-use and up-to-date bitstreams and documentation
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:books: Want to know more? Check out [_Data Sheet: Software Framework_](https://stnolting.github.io/neorv32/#_software_framework).
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## 5. Getting Started
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This overview provides some *quick links* to the most important sections of the
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[online Data Sheet](https://stnolting.github.io/neorv32) and the
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[online User Guide](https://stnolting.github.io/neorv32/ug).
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### :electric_plug: Hardware Overview
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* [Rationale](https://stnolting.github.io/neorv32/#_rationale) - NEORV32: why, how come, what for
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* [NEORV32 Processor](https://stnolting.github.io/neorv32/#_neorv32_processor_soc) - the SoC
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* [Top Entity - Signals](https://stnolting.github.io/neorv32/#_processor_top_entity_signals) - how to connect to the processor
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* [Top Entity - Generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics) - configuration options
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* [Address Space](https://stnolting.github.io/neorv32/#_address_space) - memory layout and boot configuration
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* [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - available peripheral modules and memories
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* [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - online & in-system debugging of the processor via JTAG
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* [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - the CPU
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* [RISC-V compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs. and what is not
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* [Full Virtualization](https://stnolting.github.io/neorv32/#_full_virtualization) - hardware execution safety
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* [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available RISC-V ISA extensions
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* [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers
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* [Traps](https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts) - interrupts and exceptions
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### :floppy_disk: Software Overview
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* [Example Programs](https://github.com/stnolting/neorv32/tree/master/sw/example) - test program execution on your setup
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* [Core Libraries](https://stnolting.github.io/neorv32/#_core_libraries) - high-level functions for accessing the processor's peripherals
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* [Software Framework Documentation](https://stnolting.github.io/neorv32/sw/files.html) - `doxygen`-based documentation
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* [Application Makefiles](https://stnolting.github.io/neorv32/#_application_makefile) - turning your application into an executable
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* [Bootloader](https://stnolting.github.io/neorv32/#_bootloader) - the build-in NEORV32 bootloader
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### :rocket: User Guide
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* [Toolchain Setup](https://stnolting.github.io/neorv32/ug/#_software_toolchain_setup) - install and setup RISC-V gcc
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* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - setup a new NEORV32 EDA project
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* [General Software Setup](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) - configure the software framework
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* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using `make`
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* [Upload via Bootloader](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart) - upload and execute executables
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* [Application-Specific Processor Configuration](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration) - tailor the processor to your needs
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* [Adding Custom Hardware Modules](https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules) - add _your_ custom hardware
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* [Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system*
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* [Simulation](https://stnolting.github.io/neorv32/ug/#_simulating_the_processor) - simulate the whole SoC
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* [Hello World!](https://stnolting.github.io/neorv32/ug/index.html#_hello_world) - run a quick _"hello world"_ simulation
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### :copyright: Legal
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||
[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
|
||
[](https://doi.org/10.5281/zenodo.5018888)
|
||
|
||
* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, limitation of liability for external links, proprietary notice, ...
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||
* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information
|
||
* [Impressum](https://github.com/stnolting/neorv32/blob/master/docs/impressum.md) - imprint
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## Acknowledgements
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||
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**A big shout-out goes to the community and all the [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project! :heart:**
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[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
|
||
|
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Continuous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
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