28 lines
837 B
VHDL
28 lines
837 B
VHDL
ARCHITECTURE studentVersion OF triangleToPolygon IS
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signal mySignal : unsigned(bitNb downto 0);
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constant aFullTriangle : unsigned(bitNb downto 0) := (others => '1');
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BEGIN
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convert: process(triangle)
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begin
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if (('0' & triangle) + ('0' & shift_right(triangle, 1))) < shift_right(aFullTriangle, 3) then
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mySignal <= shift_right(aFullTriangle,3);
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elsif (('0' & triangle) + ('0' & shift_right(triangle, 1))) > (shift_right(aFullTriangle, 1) + shift_right('0' & aFullTriangle, 3)) then
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mySignal <= (shift_right(aFullTriangle,1) + shift_right(aFullTriangle,3));
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elsif '1' then
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mySignal <= ('0' & triangle) + ('0' & shift_right(triangle, 1) );
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end if ;
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end process convert;
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polygon <= resize(mySignal-shift_right('0' & aFullTriangle,3), bitNb);
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END ARCHITECTURE studentVersion;
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