3972 lines
47 KiB
Plaintext
3972 lines
47 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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instances [
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(Instance
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name "I_dff"
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duLibraryName "Board"
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duName "DFF"
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elements [
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]
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mwi 0
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uid 1071,0
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)
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(Instance
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name "I_inv2"
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duLibraryName "Board"
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duName "inverterIn"
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elements [
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]
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mwi 0
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uid 1806,0
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)
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(Instance
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name "I_inv1"
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duLibraryName "Board"
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duName "inverterIn"
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elements [
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]
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mwi 0
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uid 1817,0
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)
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(Instance
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name "I_main"
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duLibraryName "Lissajous"
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duName "lissajousGenerator"
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elements [
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(GiElement
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name "signalBitNb"
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type "positive"
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value "signalBitNb"
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)
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(GiElement
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name "phaseBitNb"
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type "positive"
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value "phaseBitNb"
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)
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(GiElement
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name "stepX"
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type "positive"
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value "stepX"
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)
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(GiElement
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name "stepY"
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type "positive"
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value "stepY"
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)
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]
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mwi 0
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uid 2310,0
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)
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]
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embeddedInstances [
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(EmbeddedInstance
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name "eb4"
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number "4"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
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value " "
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)
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(vvPair
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variable "HDLDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hdl"
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)
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(vvPair
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variable "HDSDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds"
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)
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(vvPair
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variable "SideDataDesignDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajous@generator_circuit\\master@version.bd.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajous@generator_circuit\\master@version.bd.user"
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)
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(vvPair
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variable "SourceDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds"
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)
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(vvPair
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|
variable "appl"
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value "HDL Designer"
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)
|
|
(vvPair
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|
variable "arch_name"
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value "masterVersion"
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)
|
|
(vvPair
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|
variable "asm_file"
|
|
value "beamer.asm"
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|
)
|
|
(vvPair
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|
variable "concat_file"
|
|
value "concatenated"
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|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
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)
|
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(vvPair
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variable "d"
|
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajous@generator_circuit"
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)
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(vvPair
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variable "d_logical"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajousGenerator_circuit"
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)
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(vvPair
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variable "date"
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|
value "28.04.2023"
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)
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(vvPair
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variable "day"
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value "ven."
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)
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(vvPair
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variable "day_long"
|
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value "vendredi"
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)
|
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(vvPair
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variable "dd"
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value "28"
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)
|
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(vvPair
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variable "designName"
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value "$DESIGN_NAME"
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)
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(vvPair
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variable "entity_name"
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value "lissajousGenerator_circuit"
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)
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(vvPair
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variable "ext"
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value "<TBD>"
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)
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(vvPair
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variable "f"
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value "master@version.bd"
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)
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(vvPair
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variable "f_logical"
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value "masterVersion.bd"
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)
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(vvPair
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|
variable "f_noext"
|
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value "master@version"
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)
|
|
(vvPair
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variable "graphical_source_author"
|
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value "axel.amand"
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)
|
|
(vvPair
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|
variable "graphical_source_date"
|
|
value "28.04.2023"
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)
|
|
(vvPair
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|
variable "graphical_source_group"
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value "UNKNOWN"
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)
|
|
(vvPair
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|
variable "graphical_source_host"
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value "WE7860"
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)
|
|
(vvPair
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|
variable "graphical_source_time"
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value "14:46:55"
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)
|
|
(vvPair
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|
variable "group"
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value "UNKNOWN"
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)
|
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(vvPair
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|
variable "host"
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value "WE7860"
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)
|
|
(vvPair
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|
variable "language"
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value "VHDL"
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)
|
|
(vvPair
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|
variable "library"
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value "Board"
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)
|
|
(vvPair
|
|
variable "library_downstream_Concatenation"
|
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value "$HDS_PROJECT_DIR/../Board/concat"
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)
|
|
(vvPair
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variable "library_downstream_Generic_1_file"
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value "U:\\SEm_curves\\Synthesis"
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)
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|
(vvPair
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variable "library_downstream_ModelSim"
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value "D:\\Users\\ELN_labs\\VHDL_comp"
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)
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|
(vvPair
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variable "library_downstream_ModelSimCompiler"
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value "$SCRATCH_DIR/Board"
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)
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(vvPair
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variable "library_downstream_QuestaSimCompiler"
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value "$HDS_PROJECT_DIR/../Board/work"
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)
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(vvPair
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variable "library_downstream_SpyGlass"
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value "U:\\SEm_curves\\Synthesis"
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)
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(vvPair
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variable "library_downstream_SvAssistantInvoke"
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|
value "$HDS_PROJECT_DIR/../Board/svassistant"
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)
|
|
(vvPair
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variable "mm"
|
|
value "04"
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)
|
|
(vvPair
|
|
variable "module_name"
|
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value "lissajousGenerator_circuit"
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|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
|
|
)
|
|
(vvPair
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|
variable "month_long"
|
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value "avril"
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|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajous@generator_circuit\\master@version.bd"
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)
|
|
(vvPair
|
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variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajousGenerator_circuit\\masterVersion.bd"
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|
)
|
|
(vvPair
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|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
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|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
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|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "/usr/opt/Modelsim/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "bd"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "master@version"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "masterVersion"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:46:55"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "lissajousGenerator_circuit"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "masterVersion"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2023"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "23"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 83,0
|
|
optionalChildren [
|
|
*1 (PortIoIn
|
|
uid 9,0
|
|
shape (CompositeShape
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|
uid 10,0
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va (VaSet
|
|
vasetType 1
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|
fg "0,0,32768"
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)
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optionalChildren [
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|
(Pentagon
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uid 11,0
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sl 0
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ro 270
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xt "15000,29625,16500,30375"
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)
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(Line
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uid 12,0
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sl 0
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ro 270
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xt "16500,30000,17000,30000"
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pts [
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"16500,30000"
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"17000,30000"
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]
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)
|
|
]
|
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)
|
|
tg (WTG
|
|
uid 13,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 14,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
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)
|
|
xt "10200,29300,14000,30700"
|
|
st "clock"
|
|
ju 2
|
|
blo "14000,30500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*2 (Net
|
|
uid 21,0
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
declText (MLText
|
|
uid 22,0
|
|
va (VaSet
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|
)
|
|
xt "-1000,8000,11800,9200"
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st "clock : std_ulogic"
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|
)
|
|
)
|
|
*3 (PortIoOut
|
|
uid 23,0
|
|
shape (CompositeShape
|
|
uid 24,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
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)
|
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optionalChildren [
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|
(Pentagon
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uid 25,0
|
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sl 0
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ro 270
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xt "81500,25625,83000,26375"
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)
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(Line
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uid 26,0
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sl 0
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ro 270
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xt "81000,26000,81500,26000"
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pts [
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"81000,26000"
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"81500,26000"
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]
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)
|
|
]
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)
|
|
tg (WTG
|
|
uid 27,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 28,0
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va (VaSet
|
|
isHidden 1
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font "Verdana,12,0"
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)
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|
xt "84000,25300,87800,26700"
|
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st "yOut"
|
|
blo "84000,26500"
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|
tm "WireNameMgr"
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)
|
|
)
|
|
)
|
|
*4 (PortIoIn
|
|
uid 37,0
|
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shape (CompositeShape
|
|
uid 38,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
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)
|
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optionalChildren [
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(Pentagon
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uid 39,0
|
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sl 0
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ro 270
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xt "15000,41625,16500,42375"
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(Line
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uid 40,0
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sl 0
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ro 270
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xt "16500,42000,17000,42000"
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pts [
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|
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"17000,42000"
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]
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)
|
|
]
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|
)
|
|
tg (WTG
|
|
uid 41,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 42,0
|
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va (VaSet
|
|
isHidden 1
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|
font "Verdana,12,0"
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)
|
|
xt "8200,41300,14000,42700"
|
|
st "reset_N"
|
|
ju 2
|
|
blo "14000,42500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*5 (Net
|
|
uid 49,0
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 2,0
|
|
)
|
|
declText (MLText
|
|
uid 50,0
|
|
va (VaSet
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)
|
|
xt "-1000,22000,16200,23200"
|
|
st "SIGNAL reset : std_ulogic"
|
|
)
|
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)
|
|
*6 (Grouping
|
|
uid 51,0
|
|
optionalChildren [
|
|
*7 (CommentText
|
|
uid 53,0
|
|
shape (Rectangle
|
|
uid 54,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "59000,65000,76000,66000"
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|
)
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|
oxt "18000,70000,35000,71000"
|
|
text (MLText
|
|
uid 55,0
|
|
va (VaSet
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fg "0,0,32768"
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bg "0,0,32768"
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)
|
|
xt "59200,65500,59200,65500"
|
|
st "
|
|
by %user on %dd %month %year
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
*8 (CommentText
|
|
uid 56,0
|
|
shape (Rectangle
|
|
uid 57,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "76000,61000,80000,62000"
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|
)
|
|
oxt "35000,66000,39000,67000"
|
|
text (MLText
|
|
uid 58,0
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va (VaSet
|
|
fg "0,0,32768"
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|
bg "0,0,32768"
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)
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xt "76200,61500,76200,61500"
|
|
st "
|
|
Project:
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
*9 (CommentText
|
|
uid 59,0
|
|
shape (Rectangle
|
|
uid 60,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
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|
fg "65280,65280,46080"
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)
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xt "59000,63000,76000,64000"
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)
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oxt "18000,68000,35000,69000"
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|
text (MLText
|
|
uid 61,0
|
|
va (VaSet
|
|
fg "0,0,32768"
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bg "0,0,32768"
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)
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|
xt "59200,63500,59200,63500"
|
|
st "
|
|
<enter diagram title here>
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
*10 (CommentText
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uid 62,0
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shape (Rectangle
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uid 63,0
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sl 0
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va (VaSet
|
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vasetType 1
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|
fg "65280,65280,46080"
|
|
)
|
|
xt "55000,63000,59000,64000"
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)
|
|
oxt "14000,68000,18000,69000"
|
|
text (MLText
|
|
uid 64,0
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va (VaSet
|
|
fg "0,0,32768"
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bg "0,0,32768"
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)
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xt "55200,63500,55200,63500"
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|
st "
|
|
Title:
|
|
"
|
|
tm "CommentText"
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wrapOption 3
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|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
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)
|
|
*11 (CommentText
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|
uid 65,0
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shape (Rectangle
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uid 66,0
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|
sl 0
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va (VaSet
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vasetType 1
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fg "65280,65280,46080"
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)
|
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xt "76000,62000,96000,66000"
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)
|
|
oxt "35000,67000,55000,71000"
|
|
text (MLText
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|
uid 67,0
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va (VaSet
|
|
fg "0,0,32768"
|
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bg "0,0,32768"
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)
|
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xt "76200,62200,90300,63400"
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st "
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"
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tm "CommentText"
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wrapOption 3
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visibleHeight 4000
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visibleWidth 20000
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)
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ignorePrefs 1
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)
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uid 68,0
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shape (Rectangle
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uid 69,0
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sl 0
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va (VaSet
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vasetType 1
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fg "65280,65280,46080"
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)
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xt "80000,61000,96000,62000"
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)
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oxt "39000,66000,55000,67000"
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text (MLText
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uid 70,0
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va (VaSet
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fg "0,0,32768"
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bg "0,0,32768"
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)
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xt "80200,61500,80200,61500"
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st "
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"
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tm "CommentText"
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wrapOption 3
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visibleHeight 1000
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visibleWidth 16000
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)
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position 1
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ignorePrefs 1
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)
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uid 71,0
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shape (Rectangle
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uid 72,0
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sl 0
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va (VaSet
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vasetType 1
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fg "65280,65280,46080"
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)
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xt "55000,61000,76000,63000"
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)
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oxt "14000,66000,35000,68000"
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text (MLText
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uid 73,0
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va (VaSet
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fg "32768,0,0"
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)
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xt "60350,61400,70650,62600"
|
|
st "
|
|
<company name>
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|
"
|
|
ju 0
|
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tm "CommentText"
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wrapOption 3
|
|
visibleHeight 2000
|
|
visibleWidth 21000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
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)
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|
*14 (CommentText
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|
uid 74,0
|
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shape (Rectangle
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|
uid 75,0
|
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sl 0
|
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va (VaSet
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|
vasetType 1
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|
fg "65280,65280,46080"
|
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)
|
|
xt "55000,64000,59000,65000"
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)
|
|
oxt "14000,69000,18000,70000"
|
|
text (MLText
|
|
uid 76,0
|
|
va (VaSet
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|
fg "0,0,32768"
|
|
bg "0,0,32768"
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)
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xt "55200,64500,55200,64500"
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|
st "
|
|
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|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
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)
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|
*15 (CommentText
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|
uid 77,0
|
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shape (Rectangle
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|
uid 78,0
|
|
sl 0
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va (VaSet
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|
vasetType 1
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|
fg "65280,65280,46080"
|
|
)
|
|
xt "55000,65000,59000,66000"
|
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)
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|
oxt "14000,70000,18000,71000"
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text (MLText
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|
uid 79,0
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va (VaSet
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|
fg "0,0,32768"
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bg "0,0,32768"
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)
|
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xt "55200,65500,55200,65500"
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|
st "
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|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
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|
position 1
|
|
ignorePrefs 1
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)
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*16 (CommentText
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|
uid 80,0
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shape (Rectangle
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|
uid 81,0
|
|
sl 0
|
|
va (VaSet
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|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "59000,64000,76000,65000"
|
|
)
|
|
oxt "18000,69000,35000,70000"
|
|
text (MLText
|
|
uid 82,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
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)
|
|
xt "59200,64500,59200,64500"
|
|
st "
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|
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|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
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|
)
|
|
]
|
|
shape (GroupingShape
|
|
uid 52,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
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|
lineStyle 2
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|
lineWidth 2
|
|
)
|
|
xt "55000,61000,96000,66000"
|
|
)
|
|
oxt "14000,66000,55000,71000"
|
|
)
|
|
*17 (Net
|
|
uid 253,0
|
|
decl (Decl
|
|
n "reset_N"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 3,0
|
|
)
|
|
declText (MLText
|
|
uid 254,0
|
|
va (VaSet
|
|
)
|
|
xt "-1000,9200,12500,10400"
|
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st "reset_N : std_ulogic"
|
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)
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)
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*18 (PortIoOut
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|
uid 429,0
|
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shape (CompositeShape
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|
uid 430,0
|
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va (VaSet
|
|
vasetType 1
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|
fg "0,0,32768"
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)
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optionalChildren [
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|
(Pentagon
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|
uid 431,0
|
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sl 0
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ro 270
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xt "81500,29625,83000,30375"
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)
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(Line
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|
uid 432,0
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sl 0
|
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ro 270
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xt "81000,30000,81500,30000"
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pts [
|
|
"81000,30000"
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"81500,30000"
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]
|
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)
|
|
]
|
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)
|
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tg (WTG
|
|
uid 433,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 434,0
|
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va (VaSet
|
|
isHidden 1
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font "Verdana,12,0"
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)
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xt "84000,29300,92100,30700"
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|
st "triggerOut"
|
|
blo "84000,30500"
|
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tm "WireNameMgr"
|
|
)
|
|
)
|
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)
|
|
*19 (Net
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uid 441,0
|
|
decl (Decl
|
|
n "triggerOut"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 4,0
|
|
)
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|
declText (MLText
|
|
uid 442,0
|
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va (VaSet
|
|
)
|
|
xt "-1000,10400,12800,11600"
|
|
st "triggerOut : std_ulogic"
|
|
)
|
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)
|
|
*20 (Net
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|
uid 476,0
|
|
decl (Decl
|
|
n "xOut"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 6,0
|
|
)
|
|
declText (MLText
|
|
uid 477,0
|
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va (VaSet
|
|
)
|
|
xt "-1000,11600,11900,12800"
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st "xOut : std_ulogic"
|
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)
|
|
)
|
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*21 (PortIoOut
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|
uid 569,0
|
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shape (CompositeShape
|
|
uid 570,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
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)
|
|
optionalChildren [
|
|
(Pentagon
|
|
uid 571,0
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sl 0
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ro 270
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)
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(Line
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uid 572,0
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sl 0
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ro 270
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xt "81000,28000,81500,28000"
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pts [
|
|
"81000,28000"
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"81500,28000"
|
|
]
|
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)
|
|
]
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)
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tg (WTG
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|
uid 573,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
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|
uid 574,0
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va (VaSet
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|
isHidden 1
|
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font "Verdana,12,0"
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)
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xt "84000,27300,87800,28700"
|
|
st "xOut"
|
|
blo "84000,28500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*22 (Net
|
|
uid 611,0
|
|
decl (Decl
|
|
n "yOut"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 7,0
|
|
)
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|
declText (MLText
|
|
uid 612,0
|
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va (VaSet
|
|
)
|
|
xt "-1000,12800,11900,14000"
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|
st "yOut : std_ulogic"
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)
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)
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*23 (HdlText
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|
uid 818,0
|
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optionalChildren [
|
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*24 (EmbeddedText
|
|
uid 823,0
|
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commentText (CommentText
|
|
uid 824,0
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ps "CenterOffsetStrategy"
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|
shape (Rectangle
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|
uid 825,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "22000,33000,28000,35000"
|
|
)
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|
oxt "0,0,18000,5000"
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|
text (MLText
|
|
uid 826,0
|
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va (VaSet
|
|
)
|
|
xt "22200,33200,27700,34400"
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st "
|
|
logic1 <= '1';
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 2000
|
|
visibleWidth 6000
|
|
)
|
|
)
|
|
)
|
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]
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shape (Rectangle
|
|
uid 819,0
|
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va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,32768"
|
|
)
|
|
xt "21000,32000,29000,36000"
|
|
)
|
|
oxt "0,0,8000,10000"
|
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ttg (MlTextGroup
|
|
uid 820,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
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textVec [
|
|
*25 (Text
|
|
uid 821,0
|
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va (VaSet
|
|
)
|
|
xt "21400,36000,24000,37200"
|
|
st "eb4"
|
|
blo "21400,37000"
|
|
tm "HdlTextNameMgr"
|
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)
|
|
*26 (Text
|
|
uid 822,0
|
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va (VaSet
|
|
)
|
|
xt "21400,37000,22800,38200"
|
|
st "4"
|
|
blo "21400,38000"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
*27 (Net
|
|
uid 893,0
|
|
decl (Decl
|
|
n "resetSnch_N"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 10,0
|
|
)
|
|
declText (MLText
|
|
uid 894,0
|
|
va (VaSet
|
|
)
|
|
xt "-1000,23200,18300,24400"
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st "SIGNAL resetSnch_N : std_ulogic"
|
|
)
|
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)
|
|
*28 (Net
|
|
uid 895,0
|
|
decl (Decl
|
|
n "logic1"
|
|
t "std_uLogic"
|
|
o 6
|
|
suid 11,0
|
|
)
|
|
declText (MLText
|
|
uid 896,0
|
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va (VaSet
|
|
)
|
|
xt "-1000,20800,16700,22000"
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st "SIGNAL logic1 : std_uLogic"
|
|
)
|
|
)
|
|
*29 (Net
|
|
uid 897,0
|
|
decl (Decl
|
|
n "resetSynch"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 12,0
|
|
)
|
|
declText (MLText
|
|
uid 898,0
|
|
va (VaSet
|
|
)
|
|
xt "-1000,24400,17800,25600"
|
|
st "SIGNAL resetSynch : std_ulogic"
|
|
)
|
|
)
|
|
*30 (SaComponent
|
|
uid 1071,0
|
|
optionalChildren [
|
|
*31 (CptPort
|
|
uid 1054,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1055,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
isHidden 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "33250,33625,34000,34375"
|
|
)
|
|
tg (CPTG
|
|
uid 1056,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1057,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "35000,33300,36700,34700"
|
|
st "D"
|
|
blo "35000,34500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "D"
|
|
t "std_uLogic"
|
|
o 3
|
|
)
|
|
)
|
|
)
|
|
*32 (CptPort
|
|
uid 1058,0
|
|
optionalChildren [
|
|
*33 (FFT
|
|
pts [
|
|
"34750,38000"
|
|
"34000,38375"
|
|
"34000,37625"
|
|
]
|
|
uid 1062,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "34000,37625,34750,38375"
|
|
)
|
|
]
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1059,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
isHidden 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "33250,37625,34000,38375"
|
|
)
|
|
tg (CPTG
|
|
uid 1060,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1061,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "35000,37400,38200,38800"
|
|
st "CLK"
|
|
blo "35000,38600"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "CLK"
|
|
t "std_uLogic"
|
|
o 1
|
|
)
|
|
)
|
|
)
|
|
*34 (CptPort
|
|
uid 1063,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1064,0
|
|
va (VaSet
|
|
vasetType 1
|
|
isHidden 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "36625,40000,37375,40750"
|
|
)
|
|
tg (CPTG
|
|
uid 1065,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1066,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "36000,38600,39200,40000"
|
|
st "CLR"
|
|
blo "36000,39800"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "CLR"
|
|
t "std_uLogic"
|
|
o 2
|
|
)
|
|
)
|
|
)
|
|
*35 (CptPort
|
|
uid 1067,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1068,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
isHidden 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "40000,33625,40750,34375"
|
|
)
|
|
tg (CPTG
|
|
uid 1069,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1070,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "37200,33300,39000,34700"
|
|
st "Q"
|
|
ju 2
|
|
blo "39000,34500"
|
|
)
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font "Verdana,9,1"
|
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)
|
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xt "57600,33800,62800,35000"
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|
st "Lissajous"
|
|
blo "57600,34800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*60 (Text
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uid 2314,0
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va (VaSet
|
|
font "Verdana,9,1"
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)
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xt "57600,34700,68100,35900"
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|
st "lissajousGenerator"
|
|
blo "57600,35700"
|
|
tm "CptNameMgr"
|
|
)
|
|
*61 (Text
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uid 2315,0
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va (VaSet
|
|
font "Verdana,9,1"
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)
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xt "57600,35600,61700,36800"
|
|
st "I_main"
|
|
blo "57600,36600"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 2316,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
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uid 2317,0
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text (MLText
|
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uid 2318,0
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va (VaSet
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|
)
|
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xt "57000,37600,80500,42400"
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st "signalBitNb = signalBitNb ( positive )
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|
phaseBitNb = phaseBitNb ( positive )
|
|
stepX = stepX ( positive )
|
|
stepY = stepY ( positive ) "
|
|
)
|
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header ""
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)
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elements [
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|
name "signalBitNb"
|
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type "positive"
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value "signalBitNb"
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)
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(GiElement
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|
name "phaseBitNb"
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type "positive"
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value "phaseBitNb"
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)
|
|
(GiElement
|
|
name "stepX"
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|
type "positive"
|
|
value "stepX"
|
|
)
|
|
(GiElement
|
|
name "stepY"
|
|
type "positive"
|
|
value "stepY"
|
|
)
|
|
]
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)
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connectByName 1
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portVis (PortSigDisplay
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sTC 0
|
|
)
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archFileType "UNKNOWN"
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)
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*62 (Wire
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uid 16,0
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va (VaSet
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vasetType 3
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)
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xt "17000,30000,56250,30000"
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pts [
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]
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)
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start &1
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end &54
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|
sat 32
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|
eat 32
|
|
stc 0
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st 0
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sf 1
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|
si 0
|
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tg (WTG
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uid 19,0
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ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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uid 20,0
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va (VaSet
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font "Verdana,12,0"
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)
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xt "17000,28600,20800,30000"
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st "clock"
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blo "17000,29800"
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|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &2
|
|
)
|
|
*63 (Wire
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|
uid 29,0
|
|
shape (OrthoPolyLine
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|
uid 30,0
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|
va (VaSet
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|
vasetType 3
|
|
)
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xt "73750,26000,81000,26000"
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pts [
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|
"81000,26000"
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|
"73750,26000"
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|
]
|
|
)
|
|
start &3
|
|
end &57
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 33,0
|
|
ps "ConnStartEndStrategy"
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|
stg "STSignalDisplayStrategy"
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|
f (Text
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|
uid 34,0
|
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va (VaSet
|
|
font "Verdana,12,0"
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|
)
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|
xt "76000,24600,79800,26000"
|
|
st "yOut"
|
|
blo "76000,25800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &22
|
|
)
|
|
*64 (Wire
|
|
uid 43,0
|
|
shape (OrthoPolyLine
|
|
uid 44,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "17000,42000,22092,42000"
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|
pts [
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|
"17000,42000"
|
|
"22092,42000"
|
|
]
|
|
)
|
|
start &4
|
|
end &47
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 47,0
|
|
ps "ConnStartEndStrategy"
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|
stg "STSignalDisplayStrategy"
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|
f (Text
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uid 48,0
|
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va (VaSet
|
|
font "Verdana,12,0"
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)
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|
xt "16000,40600,21800,42000"
|
|
st "reset_N"
|
|
blo "16000,41800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &17
|
|
)
|
|
*65 (Wire
|
|
uid 245,0
|
|
shape (OrthoPolyLine
|
|
uid 246,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "50000,32000,56250,34000"
|
|
pts [
|
|
"50000,34000"
|
|
"53000,34000"
|
|
"53000,32000"
|
|
"56250,32000"
|
|
]
|
|
)
|
|
start &42
|
|
end &58
|
|
ss 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 251,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
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|
uid 252,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "50000,30600,58600,32000"
|
|
st "resetSynch"
|
|
blo "50000,31800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &29
|
|
)
|
|
*66 (Wire
|
|
uid 435,0
|
|
shape (OrthoPolyLine
|
|
uid 436,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "73750,30000,81000,30000"
|
|
pts [
|
|
"81000,30000"
|
|
"73750,30000"
|
|
]
|
|
)
|
|
start &18
|
|
end &55
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 439,0
|
|
ps "ConnStartEndStrategy"
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|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 440,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
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|
)
|
|
xt "76000,28600,84100,30000"
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|
st "triggerOut"
|
|
blo "76000,29800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &19
|
|
)
|
|
*67 (Wire
|
|
uid 575,0
|
|
shape (OrthoPolyLine
|
|
uid 576,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "73750,28000,81000,28000"
|
|
pts [
|
|
"81000,28000"
|
|
"73750,28000"
|
|
]
|
|
)
|
|
start &21
|
|
end &56
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 577,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 578,0
|
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va (VaSet
|
|
font "Verdana,12,0"
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|
)
|
|
xt "76000,26600,79800,28000"
|
|
st "xOut"
|
|
blo "76000,27800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &20
|
|
)
|
|
*68 (Wire
|
|
uid 873,0
|
|
shape (OrthoPolyLine
|
|
uid 874,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "32000,38000,34000,38000"
|
|
pts [
|
|
"32000,38000"
|
|
"34000,38000"
|
|
]
|
|
)
|
|
end &32
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 877,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 878,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "30000,36600,33800,38000"
|
|
st "clock"
|
|
blo "30000,37800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &2
|
|
)
|
|
*69 (Wire
|
|
uid 879,0
|
|
shape (OrthoPolyLine
|
|
uid 880,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "28000,40000,37000,42000"
|
|
pts [
|
|
"28000,42000"
|
|
"37000,42000"
|
|
"37000,40000"
|
|
]
|
|
)
|
|
start &49
|
|
end &34
|
|
ss 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 881,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 882,0
|
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va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "29000,40600,33100,42000"
|
|
st "reset"
|
|
blo "29000,41800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &5
|
|
)
|
|
*70 (Wire
|
|
uid 883,0
|
|
shape (OrthoPolyLine
|
|
uid 884,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "40000,34000,44092,34000"
|
|
pts [
|
|
"40000,34000"
|
|
"44092,34000"
|
|
]
|
|
)
|
|
start &35
|
|
end &40
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 885,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 886,0
|
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va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "39000,32600,48600,34000"
|
|
st "resetSnch_N"
|
|
blo "39000,33800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &27
|
|
)
|
|
*71 (Wire
|
|
uid 887,0
|
|
shape (OrthoPolyLine
|
|
uid 888,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "29000,34000,34000,34000"
|
|
pts [
|
|
"34000,34000"
|
|
"29000,34000"
|
|
]
|
|
)
|
|
start &31
|
|
end &23
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 891,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 892,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "30000,32600,34400,34000"
|
|
st "logic1"
|
|
blo "30000,33800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &28
|
|
)
|
|
]
|
|
bg "65535,65535,65535"
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|
grid (Grid
|
|
origin "0,0"
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|
isVisible 0
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
|
color "26368,26368,26368"
|
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)
|
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packageList *72 (PackageList
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|
uid 84,0
|
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stg "VerticalLayoutStrategy"
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textVec [
|
|
*73 (Text
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|
uid 85,0
|
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va (VaSet
|
|
font "Verdana,8,1"
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)
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|
xt "-3000,0,3900,1000"
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st "Package List"
|
|
blo "-3000,800"
|
|
)
|
|
*74 (MLText
|
|
uid 86,0
|
|
va (VaSet
|
|
)
|
|
xt "-3000,1000,14500,4600"
|
|
st "LIBRARY ieee;
|
|
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|
|
USE ieee.numeric_std.all;"
|
|
tm "PackageList"
|
|
)
|
|
]
|
|
)
|
|
compDirBlock (MlTextGroup
|
|
uid 87,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*75 (Text
|
|
uid 88,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,0,30200,1000"
|
|
st "Compiler Directives"
|
|
blo "20000,800"
|
|
)
|
|
*76 (Text
|
|
uid 89,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,1000,32200,2000"
|
|
st "Pre-module directives:"
|
|
blo "20000,1800"
|
|
)
|
|
*77 (MLText
|
|
uid 90,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,2000,32100,4400"
|
|
st "`resetall
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|
`timescale 1ns/10ps"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
*78 (Text
|
|
uid 91,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
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)
|
|
xt "20000,4000,32800,5000"
|
|
st "Post-module directives:"
|
|
blo "20000,4800"
|
|
)
|
|
*79 (MLText
|
|
uid 92,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,0,20000,0"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
*80 (Text
|
|
uid 93,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,5000,32400,6000"
|
|
st "End-module directives:"
|
|
blo "20000,5800"
|
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)
|
|
*81 (MLText
|
|
uid 94,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,6000,20000,6000"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
]
|
|
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|
|
)
|
|
windowSize "-8,-8,1928,1048"
|
|
viewArea "-4438,-1432,122918,67764"
|
|
cachedDiagramExtent "-3000,0,96000,66000"
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|
pageSetupInfo (PageSetupInfo
|
|
ptrCmd ""
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|
toPrinter 1
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|
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|
|
yMargin 48
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|
paperWidth 761
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|
paperHeight 1077
|
|
unixPaperWidth 595
|
|
unixPaperHeight 842
|
|
windowsPaperWidth 761
|
|
windowsPaperHeight 1077
|
|
paperType "A4"
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|
unixPaperName "A4 (210mm x 297mm)"
|
|
windowsPaperName "A4"
|
|
scale 75
|
|
exportedDirectories [
|
|
"$HDS_PROJECT_DIR/HTMLExport"
|
|
]
|
|
boundaryWidth 0
|
|
)
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|
hasePageBreakOrigin 1
|
|
pageBreakOrigin "-3000,0"
|
|
lastUid 2507,0
|
|
defaultCommentText (CommentText
|
|
shape (Rectangle
|
|
layer 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "0,0,15000,5000"
|
|
)
|
|
text (MLText
|
|
va (VaSet
|
|
fg "65535,0,0"
|
|
)
|
|
xt "200,200,3200,1400"
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|
st "
|
|
Text
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 4600
|
|
visibleWidth 14600
|
|
)
|
|
)
|
|
defaultRequirementText (RequirementText
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|
shape (ZoomableIcon
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|
layer 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "59904,39936,65280"
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lineColor "0,0,32768"
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)
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xt "0,0,1500,1750"
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iconMaskName "reqTracerRequirement.msk"
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)
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|
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|
|
text (MLText
|
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va (VaSet
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fg "0,0,32768"
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|
)
|
|
xt "450,2150,1450,3350"
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|
st "
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|
Text
|
|
"
|
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tm "RequirementText"
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wrapOption 3
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|
visibleHeight 1350
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visibleWidth 1100
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)
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)
|
|
defaultPanel (Panel
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "32768,0,0"
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (Text
|
|
va (VaSet
|
|
font "Verdana,10,1"
|
|
)
|
|
xt "1000,1000,4400,2200"
|
|
st "Panel0"
|
|
blo "1000,2000"
|
|
tm "PanelText"
|
|
)
|
|
)
|
|
)
|
|
defaultBlk (Blk
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "40000,56832,65535"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*82 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1700,3200,6300,4400"
|
|
st "<library>"
|
|
blo "1700,4200"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*83 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1700,4400,5800,5600"
|
|
st "<block>"
|
|
blo "1700,5400"
|
|
tm "BlkNameMgr"
|
|
)
|
|
*84 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1700,5600,2900,6800"
|
|
st "I0"
|
|
blo "1700,6600"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "1700,13200,1700,13200"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
)
|
|
defaultMWComponent (MWC
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*85 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1000,3500,3300,4500"
|
|
st "Library"
|
|
blo "1000,4300"
|
|
)
|
|
*86 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1000,4500,7000,5500"
|
|
st "MWComponent"
|
|
blo "1000,5300"
|
|
)
|
|
*87 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1000,5500,1600,6500"
|
|
st "I0"
|
|
blo "1000,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-6000,1500,-6000,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
prms (Property
|
|
pclass "params"
|
|
pname "params"
|
|
ptn "String"
|
|
)
|
|
visOptions (mwParamsVisibilityOptions
|
|
)
|
|
)
|
|
defaultSaComponent (SaComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*88 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1250,3500,3550,4500"
|
|
st "Library"
|
|
blo "1250,4300"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*89 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1250,4500,6750,5500"
|
|
st "SaComponent"
|
|
blo "1250,5300"
|
|
tm "CptNameMgr"
|
|
)
|
|
*90 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1250,5500,1850,6500"
|
|
st "I0"
|
|
blo "1250,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-5750,1500,-5750,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
defaultVhdlComponent (VhdlComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*91 (Text
|
|
va (VaSet
|
|
)
|
|
xt "950,3500,3250,4500"
|
|
st "Library"
|
|
blo "950,4300"
|
|
)
|
|
*92 (Text
|
|
va (VaSet
|
|
)
|
|
xt "950,4500,7050,5500"
|
|
st "VhdlComponent"
|
|
blo "950,5300"
|
|
)
|
|
*93 (Text
|
|
va (VaSet
|
|
)
|
|
xt "950,5500,1550,6500"
|
|
st "I0"
|
|
blo "950,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-6050,1500,-6050,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
entityPath ""
|
|
archName ""
|
|
archPath ""
|
|
)
|
|
defaultVerilogComponent (VerilogComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "-50,0,8050,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*94 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,3500,2750,4500"
|
|
st "Library"
|
|
blo "450,4300"
|
|
)
|
|
*95 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,4500,7550,5500"
|
|
st "VerilogComponent"
|
|
blo "450,5300"
|
|
)
|
|
*96 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,5500,1050,6500"
|
|
st "I0"
|
|
blo "450,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-6550,1500,-6550,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
entityPath ""
|
|
)
|
|
defaultHdlText (HdlText
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,32768"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*97 (Text
|
|
va (VaSet
|
|
)
|
|
xt "3400,4000,4600,5000"
|
|
st "eb1"
|
|
blo "3400,4800"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*98 (Text
|
|
va (VaSet
|
|
)
|
|
xt "3400,5000,3800,6000"
|
|
st "1"
|
|
blo "3400,5800"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultEmbeddedText (EmbeddedText
|
|
commentText (CommentText
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "0,0,18000,5000"
|
|
)
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "200,200,3200,1400"
|
|
st "
|
|
Text
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 4600
|
|
visibleWidth 17600
|
|
)
|
|
)
|
|
)
|
|
defaultGlobalConnector (GlobalConnector
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,0"
|
|
)
|
|
xt "-1000,-1000,1000,1000"
|
|
radius 1000
|
|
)
|
|
name (Text
|
|
va (VaSet
|
|
)
|
|
xt "-300,-500,300,500"
|
|
st "G"
|
|
blo "-300,300"
|
|
)
|
|
)
|
|
defaultRipper (Ripper
|
|
ps "OnConnectorStrategy"
|
|
shape (Line2D
|
|
pts [
|
|
"0,0"
|
|
"1000,1000"
|
|
]
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "0,0,1000,1000"
|
|
)
|
|
)
|
|
defaultBdJunction (BdJunction
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "-400,-400,400,400"
|
|
radius 400
|
|
)
|
|
)
|
|
defaultPortIoIn (PortIoIn
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "-2000,-375,-500,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "-500,0,0,0"
|
|
pts [
|
|
"-500,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "-1375,-1000,-1375,-1000"
|
|
ju 2
|
|
blo "-1375,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoOut (PortIoOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "625,-1000,625,-1000"
|
|
blo "625,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoInOut (PortIoInOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,2600,1400"
|
|
st "sig0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,3900,1400"
|
|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineStyle 3
|
|
lineWidth 1
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2600,1000"
|
|
st "bundle0"
|
|
blo "0,800"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,1500,2200"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,50000"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,0,5000,1200"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,9600,2200"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,18500,100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*99 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*100 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,11000,100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*101 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*102 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "-3000,6000,4000,7000"
|
|
st "Declarations"
|
|
blo "-3000,6800"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "-3000,7000,400,8000"
|
|
st "Ports:"
|
|
blo "-3000,7800"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "-3000,14000,1800,15000"
|
|
st "Pre User:"
|
|
blo "-3000,14800"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
)
|
|
xt "-1000,15000,19800,19800"
|
|
st "constant signalBitNb: positive := 16;
|
|
constant phaseBitNb: positive := 17;
|
|
constant stepX: positive := 3;
|
|
constant stepY: positive := 4;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "-3000,19800,6000,20800"
|
|
st "Diagram Signals:"
|
|
blo "-3000,20600"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "-3000,6000,3000,7000"
|
|
st "Post User:"
|
|
blo "-3000,6800"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-3000,6000,-3000,6000"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 19,0
|
|
usingSuid 1
|
|
emptyRow *103 (LEmptyRow
|
|
)
|
|
uid 1406,0
|
|
optionalChildren [
|
|
*104 (RefLabelRowHdr
|
|
)
|
|
*105 (TitleRowHdr
|
|
)
|
|
*106 (FilterRowHdr
|
|
)
|
|
*107 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*108 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*109 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*110 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*111 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*112 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*113 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*114 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*115 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*116 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
uid 1377,0
|
|
)
|
|
*117 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 2,0
|
|
)
|
|
)
|
|
uid 1379,0
|
|
)
|
|
*118 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "reset_N"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 3,0
|
|
)
|
|
)
|
|
uid 1381,0
|
|
)
|
|
*119 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "triggerOut"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 4,0
|
|
)
|
|
)
|
|
uid 1383,0
|
|
)
|
|
*120 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "xOut"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 6,0
|
|
)
|
|
)
|
|
uid 1387,0
|
|
)
|
|
*121 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "yOut"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 7,0
|
|
)
|
|
)
|
|
uid 1389,0
|
|
)
|
|
*122 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "resetSnch_N"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 10,0
|
|
)
|
|
)
|
|
uid 1395,0
|
|
)
|
|
*123 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "logic1"
|
|
t "std_uLogic"
|
|
o 6
|
|
suid 11,0
|
|
)
|
|
)
|
|
uid 1397,0
|
|
)
|
|
*124 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "resetSynch"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 12,0
|
|
)
|
|
)
|
|
uid 1399,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 1419,0
|
|
optionalChildren [
|
|
*125 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *126 (MRCItem
|
|
litem &103
|
|
pos 9
|
|
dimension 20
|
|
)
|
|
uid 1421,0
|
|
optionalChildren [
|
|
*127 (MRCItem
|
|
litem &104
|
|
pos 0
|
|
dimension 20
|
|
uid 1422,0
|
|
)
|
|
*128 (MRCItem
|
|
litem &105
|
|
pos 1
|
|
dimension 23
|
|
uid 1423,0
|
|
)
|
|
*129 (MRCItem
|
|
litem &106
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1424,0
|
|
)
|
|
*130 (MRCItem
|
|
litem &116
|
|
pos 0
|
|
dimension 20
|
|
uid 1378,0
|
|
)
|
|
*131 (MRCItem
|
|
litem &117
|
|
pos 5
|
|
dimension 20
|
|
uid 1380,0
|
|
)
|
|
*132 (MRCItem
|
|
litem &118
|
|
pos 1
|
|
dimension 20
|
|
uid 1382,0
|
|
)
|
|
*133 (MRCItem
|
|
litem &119
|
|
pos 2
|
|
dimension 20
|
|
uid 1384,0
|
|
)
|
|
*134 (MRCItem
|
|
litem &120
|
|
pos 3
|
|
dimension 20
|
|
uid 1388,0
|
|
)
|
|
*135 (MRCItem
|
|
litem &121
|
|
pos 4
|
|
dimension 20
|
|
uid 1390,0
|
|
)
|
|
*136 (MRCItem
|
|
litem &122
|
|
pos 6
|
|
dimension 20
|
|
uid 1396,0
|
|
)
|
|
*137 (MRCItem
|
|
litem &123
|
|
pos 7
|
|
dimension 20
|
|
uid 1398,0
|
|
)
|
|
*138 (MRCItem
|
|
litem &124
|
|
pos 8
|
|
dimension 20
|
|
uid 1400,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 1425,0
|
|
optionalChildren [
|
|
*139 (MRCItem
|
|
litem &107
|
|
pos 0
|
|
dimension 20
|
|
uid 1426,0
|
|
)
|
|
*140 (MRCItem
|
|
litem &109
|
|
pos 1
|
|
dimension 50
|
|
uid 1427,0
|
|
)
|
|
*141 (MRCItem
|
|
litem &110
|
|
pos 2
|
|
dimension 100
|
|
uid 1428,0
|
|
)
|
|
*142 (MRCItem
|
|
litem &111
|
|
pos 3
|
|
dimension 50
|
|
uid 1429,0
|
|
)
|
|
*143 (MRCItem
|
|
litem &112
|
|
pos 4
|
|
dimension 100
|
|
uid 1430,0
|
|
)
|
|
*144 (MRCItem
|
|
litem &113
|
|
pos 5
|
|
dimension 100
|
|
uid 1431,0
|
|
)
|
|
*145 (MRCItem
|
|
litem &114
|
|
pos 6
|
|
dimension 50
|
|
uid 1432,0
|
|
)
|
|
*146 (MRCItem
|
|
litem &115
|
|
pos 7
|
|
dimension 80
|
|
uid 1433,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 1420,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 1405,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *147 (LEmptyRow
|
|
)
|
|
uid 1435,0
|
|
optionalChildren [
|
|
*148 (RefLabelRowHdr
|
|
)
|
|
*149 (TitleRowHdr
|
|
)
|
|
*150 (FilterRowHdr
|
|
)
|
|
*151 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*152 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*153 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*154 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*155 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*156 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*157 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*158 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*159 (LogGeneric
|
|
generic (GiElement
|
|
name "bitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 1488,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 1447,0
|
|
optionalChildren [
|
|
*160 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *161 (MRCItem
|
|
litem &147
|
|
pos 1
|
|
dimension 20
|
|
)
|
|
uid 1449,0
|
|
optionalChildren [
|
|
*162 (MRCItem
|
|
litem &148
|
|
pos 0
|
|
dimension 20
|
|
uid 1450,0
|
|
)
|
|
*163 (MRCItem
|
|
litem &149
|
|
pos 1
|
|
dimension 23
|
|
uid 1451,0
|
|
)
|
|
*164 (MRCItem
|
|
litem &150
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1452,0
|
|
)
|
|
*165 (MRCItem
|
|
litem &159
|
|
pos 0
|
|
dimension 20
|
|
uid 1487,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 1453,0
|
|
optionalChildren [
|
|
*166 (MRCItem
|
|
litem &151
|
|
pos 0
|
|
dimension 20
|
|
uid 1454,0
|
|
)
|
|
*167 (MRCItem
|
|
litem &153
|
|
pos 1
|
|
dimension 50
|
|
uid 1455,0
|
|
)
|
|
*168 (MRCItem
|
|
litem &154
|
|
pos 2
|
|
dimension 100
|
|
uid 1456,0
|
|
)
|
|
*169 (MRCItem
|
|
litem &155
|
|
pos 3
|
|
dimension 100
|
|
uid 1457,0
|
|
)
|
|
*170 (MRCItem
|
|
litem &156
|
|
pos 4
|
|
dimension 50
|
|
uid 1458,0
|
|
)
|
|
*171 (MRCItem
|
|
litem &157
|
|
pos 5
|
|
dimension 50
|
|
uid 1459,0
|
|
)
|
|
*172 (MRCItem
|
|
litem &158
|
|
pos 6
|
|
dimension 80
|
|
uid 1460,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 1448,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 1434,0
|
|
type 1
|
|
)
|
|
activeModelName "BlockDiag"
|
|
)
|