Klagarge/SummerSchool2-Controller
Klagarge/SummerSchool2-Controller
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add bietfield for steering

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This commit is contained in:
Rémi Heredero 2023-09-05 17:43:26 +02:00
parent 8cec88d658
commit 628bbd7825
1 changed files with 34 additions and 0 deletions
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34
306-controller_interface.X/app/can_message.c
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@ -29,6 +29,31 @@ typedef union {
uint16_t full;
} BYTES_2;
typedef union{
uint16_t data;
struct{
uint8_t data[2];
}byteSplit;
struct{
unsigned b0:1;
unsigned b1:1;
unsigned b2:1;
unsigned b3:1;
unsigned b4:1;
unsigned b5:1;
unsigned b6:1;
unsigned b7:1;
unsigned b8:1;
unsigned b9:1;
unsigned b10:1;
unsigned b11:1;
unsigned b12:1;
unsigned b13:1;
unsigned b14:1;
unsigned b15:1;
}bitSplit;
} BITFIELD16;
void CM_processIncome(uint8_t idSender, uint8_t idMsg, bool rtr, uint32_t data){
BYTES_4 incomeData;
incomeData.full = data;
@ -37,6 +62,8 @@ void CM_processIncome(uint8_t idSender, uint8_t idMsg, bool rtr, uint32_t data){
revertData.separate.byte1 = incomeData.separate.byte2;
revertData.separate.byte2 = incomeData.separate.byte1;
revertData.separate.byte3 = incomeData.separate.byte0;
BITFIELD16 bField;
bField.data = (uint16_t) data;
switch(idSender){
@ -241,7 +268,14 @@ void CM_processIncome(uint8_t idSender, uint8_t idMsg, bool rtr, uint32_t data){
KART_CST.STEERING_ALIVE_TIME = MEM_read_1_byte(MEMADD_STEERING_ALIVE_TIME);
ALIVE_emitResurrect(&steering()->myChecker, 500, 0);
ALIVE_emitBorn(&steering()->myChecker, 1000, 0);
ALIVE_emitReady(&steering()->myChecker, 5000, 0);
}
if(bField.bitSplit.b4) {
if (steering()->myChecker.state == STAL_BORN){
//ALIVE_emitReady(&steering()->myChecker, 1000, 0);
}
}
}
break;