forked from HEL/circuiteria
added test diagram
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BIN
gallery/test.pdf
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BIN
gallery/test.pdf
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gallery/test.typ
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300
gallery/test.typ
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#import "../src/lib.typ": circuit, element, util, wire
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#set page(flipped: true)
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#circuit({
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element.block(
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x: 0, y: 0, w: 1.5, h: 2.2,
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id: "PC-buf",
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fill: util.colors.orange,
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ports: (
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west: (
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(id: "PCNext"),
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),
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north: (
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(id: "CLK", clock: true),
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),
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east: (
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(id: "PC"),
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),
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south: (
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(id: "EN", name: "EN"),
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)
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)
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)
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wire.stub("PC-buf-port-CLK", "north", name: "CLK")
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wire.stub("PC-buf-port-EN", "south", name: "PCWrite")
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element.multiplexer(
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x: 3, y: (from: "PC-buf-port-PC", to: "in0"), w: 1, h: 2,
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id: "AdrSrc-MP",
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fill: util.colors.orange,
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entries: 2
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)
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wire.wire(
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"wPCBuf-InstDataMgr", (
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"PC-buf-port-PC",
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"AdrSrc-MP-port-in0"
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),
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name: "PC",
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bus: true
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)
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wire.stub("AdrSrc-MP.north", "north", name: "AdrSrc")
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element.block(
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x: 6, y: (from: "AdrSrc-MP-port-out", to: "A"), w: 3, h: 4,
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id: "InstDataMgr",
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fill: util.colors.yellow,
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ports: (
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west: (
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(id: "A", name: "A"),
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(id: "WD", name: "WD")
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),
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north: (
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(id: "CLK", clock: true),
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(id: "WE", name: "WE", vertical: true),
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(id: "IRWrite", name: "IRWrite", vertical: true)
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),
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east: (
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(id: "Instr", name: "Instr."),
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(id: "RD", name: "RD")
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)
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),
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ports-margins: (
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west: (30%, 0%),
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east: (40%, 0%)
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)
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)
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wire.wire(
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"wAdrSrcMP-InstDataMgr", (
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"AdrSrc-MP-port-out",
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"InstDataMgr-port-A"
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),
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name: "Adr",
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name-pos: "end",
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bus: true
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)
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wire.stub("InstDataMgr-port-CLK", "north", name: "CLK")
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wire.stub("InstDataMgr-port-WE", "north")
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wire.stub("InstDataMgr-port-IRWrite", "north")
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wire.stub("InstDataMgr-port-WD", "west")
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element.block(
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x: 15, y: (from: "InstDataMgr-port-RD", to: "WD3"), w: 3, h: 4,
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id: "RegFile",
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fill: util.colors.pink,
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ports: (
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west: (
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(id: "A1", name: "A1"),
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(id: "A2", name: "A2"),
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(id: "A3", name: "A3"),
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(id: "WD3", name: "WD3"),
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),
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north: (
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(id: "CLK", clock: true),
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(id: "WE3", name: "WE3", vertical: true)
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),
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east: (
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(id: "RD1", name: "RD1"),
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(id: "RD2", name: "RD2"),
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)
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),
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ports-margins: (
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east: (20%, 20%)
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)
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)
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wire.stub("RegFile-port-CLK", "north", name: "CLK")
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wire.stub("RegFile-port-WE3", "north", name: "Regwrite", vertical: true)
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wire.stub("RegFile-port-A2", "west")
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wire.stub("RegFile-port-RD2", "east")
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element.extender(
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x: 15, y: -3.5, w: 3, h: 1,
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id: "Extender",
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fill: util.colors.green
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)
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wire.wire(
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"wExtender-ImmSrc", (
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"Extender.north",
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(18, -2)
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),
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style: "zigzag",
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zigzag-ratio: 0%,
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name: "ImmSrc",
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name-pos: "end",
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bus: true
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)
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let mid = ("InstDataMgr.east", 50%, "RegFile.west")
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wire.wire(
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"wInstDataMgr-Bus", (
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"InstDataMgr-port-Instr",
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(vertical: (), horizontal: mid)
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),
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name: "Instr",
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name-pos: "start",
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bus: true
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)
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wire.wire(
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"wBus", (
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(v => (v.at(0), -3.5), mid),
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(horizontal: (), vertical: (0, 3.5)),
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),
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bus: true
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)
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wire.wire(
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"wBus-RegFile-A1", (
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"RegFile-port-A1",
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(horizontal: mid, vertical: ()),
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),
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name: "RS1",
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name-pos: "end",
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slice: (19, 15),
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reverse: true,
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bus: true
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)
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wire.wire(
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"wBus-RegFile-A3", (
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"RegFile-port-A3",
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(horizontal: mid, vertical: ()),
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),
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name: "RD",
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name-pos: "end",
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slice: (11, 7),
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reverse: true,
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bus: true
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)
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wire.wire(
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"wBus-Extender", (
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"Extender-port-in",
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(horizontal: mid, vertical: ()),
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),
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slice: (31, 7),
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reverse: true,
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bus: true
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)
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element.alu(
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x: 22, y: (from: "RegFile-port-RD1", to: "in1"), w: 1, h: 2,
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id: "ALU",
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fill: util.colors.purple
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)
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wire.wire(
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"wRegFile-ALU", (
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"RegFile-port-RD1",
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"ALU-port-in1"
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),
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name: ("A", "SrcA"),
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bus: true
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)
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element.block(
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x: 26, y: (from: "ALU-port-out", to: "in"), w: 1.5, h: 2,
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id: "OutBuf",
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fill: util.colors.orange,
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ports: (
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west: (
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(id: "in"),
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),
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north: (
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(id: "CLK", clock: true),
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),
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east: (
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(id: "out"),
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)
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)
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)
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wire.stub("OutBuf-port-CLK", "north", name: "CLK")
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wire.wire(
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"wALU-OutBuf", (
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"ALU-port-out",
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"OutBuf-port-in"
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),
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name: "ALUResult",
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bus: true
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)
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element.multiplexer(
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x: 30, y: (from: "OutBuf-port-out", to: "in0"), w: 1, h: 2.5,
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id: "Res-MP",
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fill: util.colors.orange,
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entries: 3
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)
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wire.stub("Res-MP.north", "north", name: "ResultSrc")
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wire.stub("Res-MP-port-in2", "west")
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wire.wire(
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"wOutBuf-ResMP", (
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"OutBuf-port-out",
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"Res-MP-port-in0"
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),
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name: "ALUOut",
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bus: true
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)
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wire.wire(
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"wExt-ALU", (
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"Extender-port-out",
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"ALU-port-in2",
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),
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name: ("ImmExt", "SrcB"),
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bus: true,
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style: "zigzag",
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zigzag-ratio: 60%
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)
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wire.wire(
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"wInstDataMgr-ResMP", (
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"InstDataMgr-port-RD",
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"Res-MP-port-in1"
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),
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style: "dodge",
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dodge-y: -4,
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dodge-sides: ("east", "west"),
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name: "Data",
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name-pos: "start",
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bus: true
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)
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wire.wire(
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"wResMP-AdrSrc", (
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"Res-MP-port-out",
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"AdrSrc-MP-port-in1"
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),
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style: "dodge",
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dodge-y: -5,
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dodge-sides: ("east", "west"),
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dodge-margins: (0.5, 1),
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bus: true
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)
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wire.wire(
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"wResMP-RegFile", (
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"Res-MP-port-out",
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"RegFile-port-WD3"
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),
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style: "dodge",
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dodge-y: -5,
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dodge-sides: ("east", "west"),
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dodge-margins: (0.5, 1),
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bus: true
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)
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wire.wire(
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"wResMP-PCBuf", (
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"Res-MP-port-out",
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"PC-buf-port-PCNext"
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),
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style: "dodge",
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dodge-y: -5,
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dodge-sides: ("east", "west"),
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dodge-margins: (0.5, 1.5),
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name: "PCNext",
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name-pos: "end",
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bus: true
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)
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wire.intersection("wResMP-RegFile.dodge-end")
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wire.intersection("wResMP-AdrSrc.dodge-end")
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})
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