Merge pull request 'feature: add IEC gates' (#11) from bono/circuiteria:add_iec_gates into dev

Reviewed-on: HEL/circuiteria#11
Reviewed-by: Louis Heredero <louis@herdac.ch>

doc/examples.typ

@@ -115,6 +115,46 @@ gates.gate-xnor(x: 0, y: 0, w: 1.5, h: 1.5)
 gates.gate-xnor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
 ```, vertical: true)
 
+#let iec-gate-and = example(```
+gates.iec-gate-and(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-and(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-nand = example(```
+gates.iec-gate-nand(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-nand(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-or = example(```
+gates.iec-gate-or(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-or(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-nor = example(```
+gates.iec-gate-nor(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-nor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-xor = example(```
+gates.iec-gate-xor(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-xor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-xnor = example(```
+gates.iec-gate-xnor(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-xnor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-buf = example(```
+gates.iec-gate-buf(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-buf(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
+#let iec-gate-not = example(```
+gates.iec-gate-not(x: 0, y: 0, w: 1.5, h: 1.5)
+gates.iec-gate-not(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
+```, vertical: true)
+
 #let group = example(```
 element.group(
   id: "g1", name: "Group 1", stroke: (dash: "dashed"),

gallery/test7.typ

@@ -4,7 +4,7 @@
 #set page(width: auto, height: auto, margin: .5cm)
 
 #circuit({
-  element.gate-iec-buf(
+  element.iec-gate-buf(
     x: 0,
     y: 0,
     w: 2,
@@ -14,7 +14,7 @@
   )
   wire.stub("iec-buf-port-in0", "west")
 
-  element.gate-iec-not(
+  element.iec-gate-not(
     x: 3,
     y: 0,
     w: 2,
@@ -24,7 +24,7 @@
   )
   wire.stub("iec-not-port-in0", "west")
 
-  element.gate-iec-and(
+  element.iec-gate-and(
     id: "iec-and",
     x: 0,
     y: -3,
@@ -36,7 +36,7 @@
     wire.stub("iec-and-port-in" + str(i), "west")
   }
 
-  element.gate-iec-nand(
+  element.iec-gate-nand(
     id: "iec-nand",
     x: 3,
     y: -3,
@@ -48,7 +48,7 @@
     wire.stub("iec-nand-port-in" + str(i), "west")
   }
 
-  element.gate-iec-or(
+  element.iec-gate-or(
     id: "iec-or",
     x: 0,
     y: -6,
@@ -60,7 +60,7 @@
     wire.stub("iec-or-port-in" + str(i), "west")
   }
 
-  element.gate-iec-nor(
+  element.iec-gate-nor(
     id: "iec-nor",
     x: 3,
     y: -6,
@@ -72,7 +72,7 @@
     wire.stub("iec-nor-port-in" + str(i), "west")
   }
 
-  element.gate-iec-xor(
+  element.iec-gate-xor(
     id: "iec-xor",
     x: 0,
     y: -9,
@@ -84,7 +84,7 @@
     wire.stub("iec-xor-port-in" + str(i), "west")
   }
 
-  element.gate-iec-nxor(
+  element.iec-gate-xnor(
     id: "iec-nxor",
     x: 3,
     y: -9,

manual.typ

@@ -195,7 +195,12 @@ If you have installed Circuiteria directly in your project, import #link("src/li
   read("src/elements/logic/and.typ") + "\n" +
   read("src/elements/logic/buf.typ") + "\n" +
   read("src/elements/logic/or.typ") + "\n" +
-  read("src/elements/logic/xor.typ"),
+  read("src/elements/logic/xor.typ") + "\n" +
+  read("src/elements/logic/iec_gate.typ") + "\n" +
+  read("src/elements/logic/iec_and.typ") + "\n" +
+  read("src/elements/logic/iec_buf.typ") + "\n" +
+  read("src/elements/logic/iec_or.typ") + "\n" +
+  read("src/elements/logic/iec_xor.typ"),
   name: "gates",
   old-syntax: true,
   scope: (

src/element.typ

@@ -12,9 +12,9 @@
 #import "elements/logic/xor.typ": gate-xor, gate-xnor
 #import "elements/logic/buf.typ": gate-buf, gate-not
 #import "elements/logic/iec_gate.typ": iec-gate
-#import "elements/logic/iec_and.typ": gate-iec-and, gate-iec-nand
+#import "elements/logic/iec_and.typ": iec-gate-and, iec-gate-nand
-#import "elements/logic/iec_buf.typ": gate-iec-buf, gate-iec-not
+#import "elements/logic/iec_buf.typ": iec-gate-buf, iec-gate-not
-#import "elements/logic/iec_or.typ": gate-iec-or, gate-iec-nor
+#import "elements/logic/iec_or.typ": iec-gate-or, iec-gate-nor
-#import "elements/logic/iec_xor.typ": gate-iec-xor, gate-iec-nxor
+#import "elements/logic/iec_xor.typ": iec-gate-xor, iec-gate-xnor
 
 #import "elements/group.typ": group

src/elements/logic/iec_and.typ

@@ -6,8 +6,8 @@
 /// Draws an IEC-AND gate. This function is also available as `element.iec-gate-and()`
 /// 
 /// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-and
+/// #examples.iec-gate-and
-#let gate-iec-and(
+#let iec-gate-and(
   x: none,
   y: none,
   w: none,
@@ -40,8 +40,8 @@
 /// Draws an IEC-NAND gate. This function is also available as `element.iec-gate-nand()`
 /// 
 /// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-nand
+/// #examples.iec-gate-nand
-#let gate-iec-nand(
+#let iec-gate-nand(
   x: none,
   y: none,
   w: none,
@@ -55,7 +55,7 @@
     ports: false
   ),
 ) = {
-  gate-iec-and(
+  iec-gate-and(
     x: x,
     y: y,
     w: w,

src/elements/logic/iec_buf.typ

@@ -5,8 +5,8 @@
 /// Draws an IEC buffer gate. This function is also available as `element.iec-gate-buf()`
 ///
 /// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-buf
+/// #examples.iec-gate-buf
-#let gate-iec-buf(
+#let iec-gate-buf(
   x: none,
   y: none,
   w: none,
@@ -38,8 +38,8 @@
 /// Draws an IEC NOT gate. This function is also available as `element.iec-gate-not()`
 /// 
 /// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-not
+/// #examples.iec-gate-not
-#let gate-iec-not(
+#let iec-gate-not(
   x: none,
   y: none,
   w: none,
@@ -53,7 +53,7 @@
     ports: false,
   ),
 ) = {
-  gate-iec-buf(
+  iec-gate-buf(
     x: x,
     y: y,
     w: w,

src/elements/logic/iec_gate.typ

@@ -3,40 +3,20 @@
 #import "../element.typ"
 
 #let default-draw-shape(id, tl, tr, br, bl, fill, stroke, symbol) = {
-  let (x, y) = bl
+  let shapes = draw.rect(
-  let (width, height) = (tr.at(0) - x, tr.at(1) - y)
-
-  let t = (x + width / 2, y + height)
-  let b = (x + width / 2, y)
-
-  let f = draw.group(
-    name: id,
-    {
-      draw.merge-path(
     inset: 0.5em,
     fill: fill,
     stroke: stroke,
-        name: id + "-path",
+    name: id,
-        close: true,
+    bl, tr
-        {
-          draw.line(bl, tl, tr, br)
-        },
   )
-
+  shapes += draw.content(
-      draw.content(
+    id + ".center",
-        (x + width / 2, y + height / 2),
+    [*$ symbol $*]
-        padding: 0.5em,
-        align(center)[*$ symbol $*],
   )
-
+  return (shapes, tl, tr, br, bl)
-      draw.anchor("north", t) 
-      draw.anchor("south", b)
-    },
-  )
-  return (f, tl, tr, br, bl)
 }
 
-
 /// Draws a logic gate. This function is also available as `element.iec-gate()`
 ///
 /// - draw-shape (function): see #doc-ref("element.elmt")
@@ -114,18 +94,15 @@
   let space = 100% / inputs
   for i in range(inputs) {
     let pct = (i + 0.5) * space
-    let a = (tl, pct, bl)
+    let port-pos = (tl, pct, bl)
-    let b = (tr, pct, br)
-    let int-name = id + "i" + str(i)
-    draw.intersections(
-      int-name,
-      func,
-      draw.hide(draw.line(a, b))
-    )
     let port-name = "in" + str(i)
-    let port-pos = int-name + ".0"
     if inverted == "all" or port-name in inverted {
-      draw.circle(port-pos, radius: inverted-radius, anchor: "east", stroke: stroke)
+      draw.circle(
+        port-pos,
+        radius: inverted-radius,
+        anchor: "east",
+        stroke: stroke
+      )
       port-pos = (rel: (-2 * inverted-radius, 0), to: port-pos)
     }
     add-port(

src/elements/logic/iec_or.typ

@@ -4,8 +4,8 @@
 /// Draws an IEC-OR gate. This function is also available as `element.iec-gate-or()`
 /// 
 /// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-or
+/// #examples.iec-gate-or
-#let gate-iec-or(
+#let iec-gate-or(
   x: none,
   y: none,
   w: none,
@@ -37,8 +37,8 @@
 /// Draws an IEC-NOR gate. This function is also available as `element.iec-gate-nor()`
 /// 
 /// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-nor
+/// #examples.iec-gate-nor
-#let gate-iec-nor(
+#let iec-gate-nor(
   x: none,
   y: none,
   w: none,
@@ -52,7 +52,7 @@
     ports: false
   )
 ) = {
-  gate-iec-or(
+  iec-gate-or(
     x: x,
     y: y,
     w: w,

src/elements/logic/iec_xor.typ

@@ -4,8 +4,8 @@
 /// Draws an IEC-XOR gate. This function is also available as `element.iec-gate-xor()`
 /// 
 /// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-xor
+/// #examples.iec-gate-xor
-#let gate-iec-xor(
+#let iec-gate-xor(
   x: none,
   y: none,
   w: none,
@@ -34,11 +34,11 @@
   )
 }
 
-/// Draws an IEC-NXOR gate. This function is also available as `element.iec-gate-nxor()`
+/// Draws an IEC-XNOR gate. This function is also available as `element.iec-gate-xnor()`
 /// 
 /// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-nxor
+/// #examples.iec-gate-xnor
-#let gate-iec-nxor(
+#let iec-gate-xnor(
   x: none,
   y: none,
   w: none,
@@ -52,7 +52,7 @@
     ports: false
   )
 ) = {
-  gate-iec-xor(
+  iec-gate-xor(
     x: x,
     y: y,
     w: w,

src/gates.typ

@@ -4,7 +4,7 @@
 #import "elements/logic/xor.typ": gate-xor, gate-xnor
 #import "elements/logic/buf.typ": gate-buf, gate-not
 #import "elements/logic/iec_gate.typ": iec-gate
-#import "elements/logic/iec_and.typ": gate-iec-and, gate-iec-nand
+#import "elements/logic/iec_and.typ": iec-gate-and, iec-gate-nand
-#import "elements/logic/iec_or.typ": gate-iec-or, gate-iec-nor
+#import "elements/logic/iec_or.typ": iec-gate-or, iec-gate-nor
-#import "elements/logic/iec_buf.typ": gate-iec-buf, gate-iec-not
+#import "elements/logic/iec_buf.typ": iec-gate-buf, iec-gate-not
-#import "elements/logic/iec_xor.typ": gate-iec-xor, gate-iec-nxor
+#import "elements/logic/iec_xor.typ": iec-gate-xor, iec-gate-xnor