Merge branch 'dev' into comp/electrical

(no comment...)

doc/examples.typ

@@ -147,4 +147,22 @@ wire.wire("w1", ((0, 0), (1, 1)), style: "zigzag")
 wire.wire("w2", ((0, 0), (1, -.5)),
           style: "zigzag", zigzag-ratio: 80%)
 wire.intersection("w1.zig")
-```)
+```)
+
+#let capacitor = example(```
+electrical.capacitor(
+  x: 0, y: 0, w: 2, h: 1, id: "a",
+  scales: (100%, 80%), gap: 0.3
+)
+
+electrical.capacitor(
+  x: 4, y: -0.5, w: 1, h: 2, id: "b",
+  vertical: true, symbols: ([+], none)
+)
+```, vertical: true)
+
+#let resistor = example(```
+electrical.resistor(x: 0, y: 0, w: 2, h: 0.5, id: "a", zigzags: 8)
+electrical.resistor(x: 4, y: -0.5, w: 0.5, h: 2, id: "b", vertical: true)
+electrical.resistor(x: 6.5, y: 0, w: 2, h: 0.5, id: "c", zigzags: none)
+```, vertical: true)

gallery/test3.typ

@@ -81,4 +81,57 @@
   element.gate-xnor(
     x: 9, y: -6, w: 2, h: 2, id: "xnor"
   )
+
+  element.resistor(
+    x: 0, y: -8, w: 2, h: 0.5, id: "res1"
+  )
+
+  element.capacitor(
+    x: 3, y: (from: "res1-port-1", to: "0"),
+    w: 2, h: 0.6,
+    id: "cap1",
+    scales: (100%, 80%),
+    symbols: ([+], [-])
+  )
+
+  element.resistor(
+    x: (rel: 1, to: "cap1-port-1"),
+    y: (from: "cap1-port-1", to: "0"),
+    w: 0.5, h: 2,
+    id: "res2",
+    vertical: true,
+    zigzags: 8
+  )
+
+  element.capacitor(
+    x: (rel: 1, to: "res2.east"),
+    y: (from: "res2-port-1", to: "1"),
+    w: 0.5, h: 2,
+    id: "cap2",
+    vertical: true,
+    symbols: ([a], [b])
+  )
+
+  element.resistor(
+    x: (rel: 1, to: "cap2-port-0"),
+    y: (from: "cap2-port-0", to: "0"),
+    w: 2, h: 0.5,
+    id: "res3",
+    zigzags: none
+  )
+
+  element.resistor(
+    x: (rel: 1, to: "res3-port-1"),
+    y: (from: "res3-port-1", to: "0"),
+    w: 0.5, h: 2,
+    id: "res4",
+    zigzags: none,
+    vertical: true
+  )
+
+  wire.wire("w4", ("res1-port-1", "cap1-port-0"))
+  wire.wire("w5", ("cap1-port-1", "res2-port-0"))
+  wire.wire("w6", ("res2-port-1", "cap2-port-1"))
+  wire.wire("w7", ("cap2-port-0", "res3-port-0"))
+  wire.wire("w8", ("res3-port-1", "res4-port-0"))
 })

gallery/test7.typ

@@ -1,98 +0,0 @@
-#import "@preview/cetz:0.3.2": draw
-#import "../src/lib.typ": circuit, element, util, wire
-
-#set page(width: auto, height: auto, margin: .5cm)
-
-#circuit({
-  element.gate-iec-buf(
-    x: 0,
-    y: 0,
-    w: 2,
-    h: 2,
-    id: "iec-buf",
-    inputs: 1,
-  )
-  wire.stub("iec-buf-port-in0", "west")
-
-  element.gate-iec-not(
-    x: 3,
-    y: 0,
-    w: 2,
-    h: 2,
-    id: "iec-not",
-    inputs: 1,
-  )
-  wire.stub("iec-not-port-in0", "west")
-
-  element.gate-iec-and(
-    id: "iec-and",
-    x: 0,
-    y: -3,
-    w: 2,
-    h: 2,
-    inputs: 2,
-  )
-  for i in range(2) {
-    wire.stub("iec-and-port-in" + str(i), "west")
-  }
-
-  element.gate-iec-nand(
-    id: "iec-nand",
-    x: 3,
-    y: -3,
-    w: 2,
-    h: 2,
-    inputs: 2,
-  )
-  for i in range(2) {
-    wire.stub("iec-nand-port-in" + str(i), "west")
-  }
-
-  element.gate-iec-or(
-    id: "iec-or",
-    x: 0,
-    y: -6,
-    w: 2,
-    h: 2,
-    inputs: 2,
-  )
-  for i in range(2) {
-    wire.stub("iec-or-port-in" + str(i), "west")
-  }
-
-  element.gate-iec-nor(
-    id: "iec-nor",
-    x: 3,
-    y: -6,
-    w: 2,
-    h: 2,
-    inputs: 2,
-  )
-  for i in range(2) {
-    wire.stub("iec-nor-port-in" + str(i), "west")
-  }
-
-  element.gate-iec-xor(
-    id: "iec-xor",
-    x: 0,
-    y: -9,
-    w: 2,
-    h: 2,
-    inputs: 2,
-  )
-  for i in range(2) {
-    wire.stub("iec-xor-port-in" + str(i), "west")
-  }
-
-  element.gate-iec-nxor(
-    id: "iec-nxor",
-    x: 3,
-    y: -9,
-    w: 2,
-    h: 2,
-    inputs: 2,
-  )
-  for i in range(2) {
-    wire.stub("iec-nxor-port-in" + str(i), "west")
-  }
-})

manual.typ

@@ -4,6 +4,7 @@
 #import "doc/examples.typ"
 #import "src/circuit.typ": circuit
 #import "src/element.typ"
+#import "src/electrical.typ"
 #import "src/gates.typ"
 #import "src/util.typ"
 #import "src/wire.typ"
@@ -210,4 +211,24 @@ If you have installed Circuiteria directly in your project, import #link("src/li
   )
 )
 
-#tidy.show-module(gates-docs, sort-functions: false)
+#tidy.show-module(gates-docs, sort-functions: false)
+
+#pagebreak()
+
+#let electrical-docs = tidy.parse-module(
+  read("src/elements/electrical/capacitor.typ") + "\n" +
+  read("src/elements/electrical/resistor.typ") + "\n",
+  name: "electrical",
+  scope: (
+    element: element,
+    circuit: circuit,
+    electrical: electrical,
+    draw: draw,
+    wire: wire,
+    tidy: tidy,
+    examples: examples,
+    doc-ref: doc-ref
+  )
+)
+
+#tidy.show-module(electrical-docs, sort-functions: false)

src/electrical.typ

@@ -0,0 +1,2 @@
+#import "elements/electrical/capacitor.typ": capacitor
+#import "elements/electrical/resistor.typ": resistor

src/element.typ

@@ -11,10 +11,8 @@
 #import "elements/logic/or.typ": gate-or, gate-nor
 #import "elements/logic/xor.typ": gate-xor, gate-xnor
 #import "elements/logic/buf.typ": gate-buf, gate-not
-#import "elements/logic/iec_gate.typ": iec-gate
+
-#import "elements/logic/iec_and.typ": gate-iec-and, gate-iec-nand
+#import "elements/electrical/resistor.typ": resistor
-#import "elements/logic/iec_buf.typ": gate-iec-buf, gate-iec-not
+#import "elements/electrical/capacitor.typ": capacitor
-#import "elements/logic/iec_or.typ": gate-iec-or, gate-iec-nor
-#import "elements/logic/iec_xor.typ": gate-iec-xor, gate-iec-nxor
 
 #import "elements/group.typ": group

src/elements/electrical/capacitor.typ

@@ -0,0 +1,138 @@
+#import "@preview/cetz:0.2.2": draw
+#import "../element.typ"
+#import "../ports.typ": add-port
+
+#let draw-shape(
+  id, tl, tr, br, bl,
+  fill, stroke,
+  vertical: false,
+  gap: 0.2,
+  scales: (100%, 100%),
+  symbols: (none, none)
+) = {
+  let (x0, y0) = tl
+  let (x1, y1) = br
+
+  let w = x1 - x0
+  let h = y1 - y0
+
+  let (o0, s0) = if vertical {(y0, h)} else {(x0, w)}
+  let (o1, s1) = if vertical {(x0, w)} else {(y0, h)}
+  let m1 = o1 + s1 / 2
+
+  let pt(i, j) = if vertical {
+    (j, i)
+  } else {
+    (i, j)
+  }
+
+  let size0 = s1 * scales.first() / 100%
+  let size1 = s1 * scales.last() / 100%
+
+  if type(gap) == ratio {
+    gap = gap / 100%
+  } else {
+    gap = gap / calc.abs(s0)
+  }
+  let r0 = 0.5 - gap / 2
+  let r1 = 0.5 + gap / 2
+
+  // Coordinates in (main axis, secondary axis) format
+  let p0 = pt(o0, m1)
+  let p1 = pt(o0 + r0 * s0, m1)
+  let p2 = pt(o0 + r1 * s0, m1)
+  let p3 = pt(o0 + s0, m1)
+  
+  let p4 = pt(o0 + r0 * s0, m1 - size0 / 2)
+  let p5 = pt(o0 + r0 * s0, m1 + size0 / 2)
+  
+  let p6 = pt(o0 + r1 * s0, m1 - size1 / 2)
+  let p7 = pt(o0 + r1 * s0, m1 + size1 / 2)
+
+  let line = draw.line.with(stroke: stroke)
+  let f = draw.group(name: id, {
+    line(p0, p1)
+    line(p2, p3)
+    line(p4, p5)
+    line(p6, p7)
+
+    if symbols.first() != none {
+      draw.content(
+        p1,
+        symbols.first(),
+        anchor: if vertical {"south-west"} else {"south-east"},
+        padding: 2pt
+      )
+    }
+
+    if symbols.last() != none {
+      draw.content(
+        p2,
+        symbols.last(),
+        anchor: if vertical {"north-west"} else {"south-west"},
+        padding: 2pt
+      )
+    }
+  })
+
+  return (f, tl, tr, br, bl)
+}
+
+/// Draws a capacitor
+///
+/// #examples.capacitor
+/// For other parameters description, see #doc-ref("element.elmt")
+/// - vertical (bool): Whether the element is vertical or horizontal.
+///   - If false, port 0 is placed on the west side and port 1 on the east.\
+///   - If true, they are on the north, respectively the south sides
+/// - gap (number, ratio): The gap between both sides
+///   - if it is a number (int or float), it is interpreted as an absolute canvas-unit length
+///   - if it is a ratio, it is interpreted as proportional to the capacitor's length (width if horizontal, height if vertical)
+/// - scales (array): A pair of ratios, the sizes of the sides relative to the capacitor's height (width if vertical).
+/// - symbols (array): A pair of content or strings (or none values) to attach on the sides of the capacitor
+#let capacitor(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  name: none,
+  name-anchor: "center",
+  vertical: false,
+  gap: 0.2,
+  scales: (100%, 100%),
+  symbols: (none, none),
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  debug: (
+    ports: false
+  )
+) = {
+  let ports = if vertical {(
+    north: ((id: "0"),),
+    south: ((id: "1"),)
+  )} else {(
+    west: ((id: "0"),),
+    east: ((id: "1"),)
+  )}
+  
+  element.elmt(
+    draw-shape: draw-shape.with(
+      vertical: vertical,
+      gap: gap,
+      scales: scales,
+      symbols: symbols
+    ),
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    name: name,
+    name-anchor: name-anchor,
+    ports: ports,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    debug: debug
+  )
+}

src/elements/electrical/resistor.typ

@@ -0,0 +1,106 @@
+#import "@preview/cetz:0.2.2": draw
+#import "../element.typ"
+#import "../ports.typ": add-port
+
+#let draw-shape(
+  id, tl, tr, br, bl,
+  fill, stroke,
+  zigzags: 6,
+  vertical: false
+) = {
+  let (x0, y0) = tl
+  let (x1, y1) = br
+
+  let w = x1 - x0
+  let h = y1 - y0
+
+  let (o0, s0) = if vertical {(y0, h)} else {(x0, w)}
+  let (o1, s1) = if vertical {(x0, w)} else {(y0, h)}
+  let m1 = o1 + s1 / 2
+
+  let pt(i, j) = if vertical {
+    (j, i)
+  } else {
+    (i, j)
+  }
+
+  let p0 = pt(o0, m1)
+  let p1 = pt(o0 + 0.2 * s0, m1)
+  let p2 = pt(o0 + 0.8 * s0, m1)
+  let p3 = pt(o0 + s0, m1)
+
+  if zigzags == none {
+    let p4 = pt(o0 + 0.2 * s0, o1)
+    let p5 = pt(o0 + 0.8 * s0, o1 + s1)
+    let f = draw.group(name: id, {
+      draw.line(p0, p1)
+      draw.line(p2, p3)
+      draw.rect(p4, p5, stroke: stroke, fill: fill)
+    })
+    return (f, tl, tr, br, bl)
+  }
+  
+  let pts = (p0, p1)
+  
+  for i in range(zigzags) {
+    let r = ((i+0.5) / zigzags * 0.6 + 0.2)
+    let pos = pt(o0 + r * s0, o1 + s1 * calc.rem(i, 2))
+    pts.push(pos)
+  }
+
+  pts += (p2, p3)
+
+  let f = draw.group(name: id, {
+    draw.line(..pts, stroke: stroke)
+  })
+  return (f, tl, tr, br, bl)
+}
+
+/// Draws a resistor
+///
+/// #examples.resistor
+/// For other parameters description, see #doc-ref("element.elmt")
+/// - vertical (bool): Whether the element is vertical or horizontal. If false, port 0 is placed on the west side and port 1 on the east. If true, they are on the north, respectively the south sides
+/// - zigzags (number, none): Number of zigzags to draw. If none, a rectangle is drawn
+#let resistor(
+  x: none,
+  y: none,
+  w: none,
+  h: none,
+  name: none,
+  name-anchor: "center",
+  vertical: false,
+  zigzags: 6,
+  fill: none,
+  stroke: black + 1pt,
+  id: "",
+  debug: (
+    ports: false
+  )
+) = {
+  let ports = if vertical {(
+    north: ((id: "0"),),
+    south: ((id: "1"),)
+  )} else {(
+    west: ((id: "0"),),
+    east: ((id: "1"),)
+  )}
+
+  element.elmt(
+    draw-shape: draw-shape.with(
+      vertical: vertical,
+      zigzags: zigzags
+    ),
+    x: x,
+    y: y,
+    w: w,
+    h: h,
+    name: name,
+    name-anchor: name-anchor,
+    ports: ports,
+    fill: fill,
+    stroke: stroke,
+    id: id,
+    debug: debug
+  )
+}

src/elements/logic/iec_and.typ

@@ -1,70 +0,0 @@
-#import "@preview/cetz:0.3.2": draw
-// #import "iec_gate.typ" as iec-gate
-#import "iec_gate.typ" as iec-gate
-
-
-/// Draws an IEC-AND gate. This function is also available as `element.iec-gate-and()`
-/// 
-/// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-and
-#let gate-iec-and(
-  x: none,
-  y: none,
-  w: none,
-  h: none,
-  inputs: 2,
-  fill: none,
-  stroke: black + 1pt,
-  id: "",
-  inverted: (),
-  debug: (
-    ports: false
-  ),
-) = {
-  iec-gate.iec-gate(
-    x: x,
-    y: y,
-    w: w,
-    h: h,
-    inputs: inputs,
-    fill: fill,
-    stroke: stroke,
-    id: id,
-    inverted: inverted,
-    debug: debug,
-    symbol: $amp$,
-  )
-
-}
-
-/// Draws an IEC-NAND gate. This function is also available as `element.iec-gate-nand()`
-/// 
-/// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-nand
-#let gate-iec-nand(
-  x: none,
-  y: none,
-  w: none,
-  h: none,
-  inputs: 2,
-  fill: none,
-  stroke: black + 1pt,
-  id: "",
-  inverted: (),
-  debug: (
-    ports: false
-  ),
-) = {
-  gate-iec-and(
-    x: x,
-    y: y,
-    w: w,
-    h: h,
-    inputs: inputs,
-    fill: fill,
-    stroke: stroke,
-    id: id,
-    inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
-    debug: debug,
-  )
-}

src/elements/logic/iec_buf.typ

@@ -1,68 +0,0 @@
-#import "@preview/cetz:0.3.2": draw
-#import "iec_gate.typ" as iec-gate
-
-
-/// Draws an IEC buffer gate. This function is also available as `element.iec-gate-buf()`
-///
-/// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-buf
-#let gate-iec-buf(
-  x: none,
-  y: none,
-  w: none,
-  h: none,
-  inputs: 2,
-  fill: none,
-  stroke: black + 1pt,
-  id: "",
-  inverted: (),
-  debug: (
-    ports: false,
-  ),
-) = {
-  iec-gate.iec-gate(
-    x: x,
-    y: y,
-    w: w,
-    h: h,
-    inputs: inputs,
-    fill: fill,
-    stroke: stroke,
-    id: id,
-    inverted: inverted,
-    debug: debug,
-    symbol: "1",
-  )
-}
-
-/// Draws an IEC NOT gate. This function is also available as `element.iec-gate-not()`
-/// 
-/// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-not
-#let gate-iec-not(
-  x: none,
-  y: none,
-  w: none,
-  h: none,
-  inputs: 2,
-  fill: none,
-  stroke: black + 1pt,
-  id: "",
-  inverted: (),
-  debug: (
-    ports: false,
-  ),
-) = {
-  gate-iec-buf(
-    x: x,
-    y: y,
-    w: w,
-    h: h,
-    inputs: inputs,
-    fill: fill,
-    stroke: stroke,
-    id: id,
-    inverted: if inverted != "all" { inverted + ("out",) } else { inverted },
-    debug: debug,
-  )
-}

src/elements/logic/iec_gate.typ

@@ -1,148 +0,0 @@
-#import "@preview/cetz:0.3.2": draw, coordinate
-#import "../ports.typ": add-ports, add-port
-#import "../element.typ"
-
-#let default-draw-shape(id, tl, tr, br, bl, fill, stroke, symbol) = {
-  let (x, y) = bl
-  let (width, height) = (tr.at(0) - x, tr.at(1) - y)
-
-  let t = (x + width / 2, y + height)
-  let b = (x + width / 2, y)
-
-  let f = draw.group(
-    name: id,
-    {
-      draw.merge-path(
-        inset: 0.5em,
-        fill: fill,
-        stroke: stroke,
-        name: id + "-path",
-        close: true,
-        {
-          draw.line(bl, tl, tr, br)
-        },
-      )
-
-      draw.content(
-        (x + width / 2, y + height / 2),
-        padding: 0.5em,
-        align(center)[*$ symbol $*],
-      )
-
-      draw.anchor("north", t) 
-      draw.anchor("south", b)
-    },
-  )
-  return (f, tl, tr, br, bl)
-}
-
-
-/// Draws a logic gate. This function is also available as `element.iec-gate()`
-///
-/// - draw-shape (function): see #doc-ref("element.elmt")
-/// - x (number, dictionary): see #doc-ref("element.elmt")
-/// - y (number, dictionary): see #doc-ref("element.elmt")
-/// - w (number): see #doc-ref("element.elmt")
-/// - h (number): see #doc-ref("element.elmt")
-/// - inputs (int): The number of inputs
-/// - fill (none, color): see #doc-ref("element.elmt")
-/// - stroke (stroke): see #doc-ref("element.elmt")
-/// - id (str): see #doc-ref("element.elmt")
-/// - inverted (str, array): Either "all" or an array of port ids to display as inverted
-/// - inverted-radius (number): The radius of inverted ports dot
-/// - debug (dictionary): see #doc-ref("element.elmt")
-/// - symbol (str): The symbol to display at the center of the gate
-#let iec-gate(
-  draw-shape: default-draw-shape,
-  x: none,
-  y: none,
-  w: none,
-  h: none,
-  inputs: 2,
-  fill: none,
-  stroke: black + 1pt,
-  id: "",
-  inverted: (),
-  inverted-radius: 0.1,
-  debug: (
-    ports: false
-  ),
-  symbol: "",
-) = draw.get-ctx(ctx => {
-  let width = w
-  let height = h
-
-  let x = x
-  let y = y
-  if x == none { panic("Parameter x must be set") }
-  if y == none { panic("Parameter y must be set") }
-  if w == none { panic("Parameter w must be set") }
-  if h == none { panic("Parameter h must be set") }
-
-  if (type(x) == dictionary) {
-    let offset = x.rel
-    let to = x.to
-    let (ctx, to-pos) = coordinate.resolve(ctx, (rel: (offset, 0), to: to))
-    x = to-pos.at(0)
-  }
-  
-  if (type(y) == dictionary) {
-    let from = y.from
-    let to = y.to
-    
-    let dy
-    if to == "out" {
-      dy = height / 2
-    } else {
-      dy = height * (i + 0.5) / inputs
-    }
-    
-    let (ctx, from-pos) = coordinate.resolve(ctx, from)
-    y = from-pos.at(1) + dy - height
-  }
-
-  let tl = (x, y + height)
-  let tr = (x + width, y + height)
-  let br = (x + width, y)
-  let bl = (x, y)
-
-  // Workaround because CeTZ needs to have all draw functions in the body
-  let func = {}
-  (func, tl, tr, br, bl) = draw-shape(id, tl, tr, br, bl, fill, stroke, symbol)
-  func
-
-  let space = 100% / inputs
-  for i in range(inputs) {
-    let pct = (i + 0.5) * space
-    let a = (tl, pct, bl)
-    let b = (tr, pct, br)
-    let int-name = id + "i" + str(i)
-    draw.intersections(
-      int-name,
-      func,
-      draw.hide(draw.line(a, b))
-    )
-    let port-name = "in" + str(i)
-    let port-pos = int-name + ".0"
-    if inverted == "all" or port-name in inverted {
-      draw.circle(port-pos, radius: inverted-radius, anchor: "east", stroke: stroke)
-      port-pos = (rel: (-2 * inverted-radius, 0), to: port-pos)
-    }
-    add-port(
-      id, "west",
-      (id: port-name), port-pos,
-      debug: debug.ports
-    )
-  }
-
-  let out-pos = id + ".east"
-  if inverted == "all" or "out" in inverted {
-    draw.circle(out-pos, radius: inverted-radius, anchor: "west", stroke: stroke)
-    out-pos = (rel: (2 * inverted-radius, 0), to: out-pos)
-  }
-  add-port(
-    id, "east",
-    (id: "out"), out-pos,
-    debug: debug.ports
-  )
-})

src/elements/logic/iec_or.typ

@@ -1,67 +0,0 @@
-#import "@preview/cetz:0.3.2": draw
-#import "iec_gate.typ" as iec-gate
-
-/// Draws an IEC-OR gate. This function is also available as `element.iec-gate-or()`
-/// 
-/// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-or
-#let gate-iec-or(
-  x: none,
-  y: none,
-  w: none,
-  h: none,
-  inputs: 2,
-  fill: none,
-  stroke: black + 1pt,
-  id: "",
-  inverted: (),
-  debug: (
-    ports: false
-  )
-) = {
-  iec-gate.iec-gate(
-    x: x,
-    y: y,
-    w: w,
-    h: h,
-    inputs: inputs,
-    fill: fill,
-    stroke: stroke,
-    id: id,
-    inverted: inverted,
-    debug: debug,
-    symbol: $>= 1$,
-  )
-}
-
-/// Draws an IEC-NOR gate. This function is also available as `element.iec-gate-nor()`
-/// 
-/// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-nor
-#let gate-iec-nor(
-  x: none,
-  y: none,
-  w: none,
-  h: none,
-  inputs: 2,
-  fill: none,
-  stroke: black + 1pt,
-  id: "",
-  inverted: (),
-  debug: (
-    ports: false
-  )
-) = {
-  gate-iec-or(
-    x: x,
-    y: y,
-    w: w,
-    h: h,
-    inputs: inputs,
-    fill: fill,
-    stroke: stroke,
-    id: id,
-    inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
-    debug: debug
-  )
-}

src/elements/logic/iec_xor.typ

@@ -1,67 +0,0 @@
-#import "@preview/cetz:0.3.2": draw
-#import "iec_gate.typ" as iec-gate
-
-/// Draws an IEC-XOR gate. This function is also available as `element.iec-gate-xor()`
-/// 
-/// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-xor
-#let gate-iec-xor(
-  x: none,
-  y: none,
-  w: none,
-  h: none,
-  inputs: 2,
-  fill: none,
-  stroke: black + 1pt,
-  id: "",
-  inverted: (),
-  debug: (
-    ports: false
-  )
-) = {
-  iec-gate.iec-gate(
-    x: x,
-    y: y,
-    w: w,
-    h: h,
-    inputs: inputs,
-    fill: fill,
-    stroke: stroke,
-    id: id,
-    inverted: inverted,
-    debug: debug,
-    symbol: $= 1$,
-  )
-}
-
-/// Draws an IEC-NXOR gate. This function is also available as `element.iec-gate-nxor()`
-/// 
-/// For parameters, see #doc-ref("gates.iec-gate")
-/// #examples.gate-iec-nxor
-#let gate-iec-nxor(
-  x: none,
-  y: none,
-  w: none,
-  h: none,
-  inputs: 2,
-  fill: none,
-  stroke: black + 1pt,
-  id: "",
-  inverted: (),
-  debug: (
-    ports: false
-  )
-) = {
-  gate-iec-xor(
-    x: x,
-    y: y,
-    w: w,
-    h: h,
-    inputs: inputs,
-    fill: fill,
-    stroke: stroke,
-    id: id,
-    inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
-    debug: debug
-  )
-}

src/gates.typ

@@ -2,9 +2,4 @@
 #import "elements/logic/and.typ": gate-and, gate-nand
 #import "elements/logic/or.typ": gate-or, gate-nor
 #import "elements/logic/xor.typ": gate-xor, gate-xnor
-#import "elements/logic/buf.typ": gate-buf, gate-not
+#import "elements/logic/buf.typ": gate-buf, gate-not
-#import "elements/logic/iec_gate.typ": iec-gate
-#import "elements/logic/iec_and.typ": gate-iec-and, gate-iec-nand
-#import "elements/logic/iec_or.typ": gate-iec-or, gate-iec-nor
-#import "elements/logic/iec_buf.typ": gate-iec-buf, gate-iec-not
-#import "elements/logic/iec_xor.typ": gate-iec-xor, gate-iec-nxor

src/lib.typ

@@ -1,6 +1,7 @@
 #let version = version(0, 2, 0)
 
 #import "circuit.typ": circuit
+#import "electrical.typ"
 #import "element.typ"
 #import "gates.typ"
 #import "util.typ"