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comp/elect
...
9966656e8b
| Author | SHA1 | Date | |
|---|---|---|---|
| 9966656e8b | |||
| 3ccb79c6c2 |
@ -148,21 +148,3 @@ wire.wire("w2", ((0, 0), (1, -.5)),
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style: "zigzag", zigzag-ratio: 80%)
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wire.intersection("w1.zig")
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```)
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#let capacitor = example(```
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electrical.capacitor(
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x: 0, y: 0, w: 2, h: 1, id: "a",
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scales: (100%, 80%), gap: 0.3
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)
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electrical.capacitor(
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x: 4, y: -0.5, w: 1, h: 2, id: "b",
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vertical: true, symbols: ([+], none)
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)
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```, vertical: true)
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#let resistor = example(```
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electrical.resistor(x: 0, y: 0, w: 2, h: 0.5, id: "a", zigzags: 8)
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electrical.resistor(x: 4, y: -0.5, w: 0.5, h: 2, id: "b", vertical: true)
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electrical.resistor(x: 6.5, y: 0, w: 2, h: 0.5, id: "c", zigzags: none)
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```, vertical: true)
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Before Width: | Height: | Size: 81 KiB After Width: | Height: | Size: 66 KiB |
@ -81,57 +81,4 @@
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element.gate-xnor(
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x: 9, y: -6, w: 2, h: 2, id: "xnor"
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)
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element.resistor(
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x: 0, y: -8, w: 2, h: 0.5, id: "res1"
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)
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element.capacitor(
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x: 3, y: (from: "res1-port-1", to: "0"),
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w: 2, h: 0.6,
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id: "cap1",
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scales: (100%, 80%),
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symbols: ([+], [-])
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)
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element.resistor(
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x: (rel: 1, to: "cap1-port-1"),
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y: (from: "cap1-port-1", to: "0"),
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w: 0.5, h: 2,
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id: "res2",
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vertical: true,
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zigzags: 8
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)
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element.capacitor(
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x: (rel: 1, to: "res2.east"),
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y: (from: "res2-port-1", to: "1"),
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w: 0.5, h: 2,
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id: "cap2",
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vertical: true,
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symbols: ([a], [b])
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)
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element.resistor(
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x: (rel: 1, to: "cap2-port-0"),
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y: (from: "cap2-port-0", to: "0"),
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w: 2, h: 0.5,
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id: "res3",
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zigzags: none
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)
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element.resistor(
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x: (rel: 1, to: "res3-port-1"),
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y: (from: "res3-port-1", to: "0"),
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w: 0.5, h: 2,
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id: "res4",
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zigzags: none,
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vertical: true
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)
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wire.wire("w4", ("res1-port-1", "cap1-port-0"))
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wire.wire("w5", ("cap1-port-1", "res2-port-0"))
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wire.wire("w6", ("res2-port-1", "cap2-port-1"))
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wire.wire("w7", ("cap2-port-0", "res3-port-0"))
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wire.wire("w8", ("res3-port-1", "res4-port-0"))
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})
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BIN
gallery/test7.pdf
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BIN
gallery/test7.pdf
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BIN
gallery/test7.png
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BIN
gallery/test7.png
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After Width: | Height: | Size: 34 KiB |
98
gallery/test7.typ
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98
gallery/test7.typ
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@ -0,0 +1,98 @@
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#import "@preview/cetz:0.3.2": draw
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#import "../src/lib.typ": circuit, element, util, wire
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#set page(width: auto, height: auto, margin: .5cm)
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#circuit({
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element.gate-iec-buf(
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x: 0,
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y: 0,
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w: 2,
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h: 2,
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id: "iec-buf",
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inputs: 1,
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)
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wire.stub("iec-buf-port-in0", "west")
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element.gate-iec-not(
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x: 3,
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y: 0,
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w: 2,
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h: 2,
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id: "iec-not",
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inputs: 1,
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)
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wire.stub("iec-not-port-in0", "west")
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element.gate-iec-and(
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id: "iec-and",
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x: 0,
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y: -3,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-and-port-in" + str(i), "west")
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}
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element.gate-iec-nand(
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id: "iec-nand",
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x: 3,
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y: -3,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-nand-port-in" + str(i), "west")
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}
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element.gate-iec-or(
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id: "iec-or",
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x: 0,
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y: -6,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-or-port-in" + str(i), "west")
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}
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element.gate-iec-nor(
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id: "iec-nor",
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x: 3,
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y: -6,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-nor-port-in" + str(i), "west")
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}
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element.gate-iec-xor(
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id: "iec-xor",
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x: 0,
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y: -9,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-xor-port-in" + str(i), "west")
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}
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element.gate-iec-nxor(
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id: "iec-nxor",
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x: 3,
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y: -9,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-nxor-port-in" + str(i), "west")
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}
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})
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BIN
manual.pdf
BIN
manual.pdf
Binary file not shown.
21
manual.typ
21
manual.typ
@ -4,7 +4,6 @@
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#import "doc/examples.typ"
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#import "src/circuit.typ": circuit
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#import "src/element.typ"
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#import "src/electrical.typ"
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#import "src/gates.typ"
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#import "src/util.typ"
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#import "src/wire.typ"
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@ -212,23 +211,3 @@ If you have installed Circuiteria directly in your project, import #link("src/li
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)
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#tidy.show-module(gates-docs, sort-functions: false)
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#pagebreak()
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#let electrical-docs = tidy.parse-module(
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read("src/elements/electrical/capacitor.typ") + "\n" +
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read("src/elements/electrical/resistor.typ") + "\n",
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name: "electrical",
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scope: (
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element: element,
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circuit: circuit,
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electrical: electrical,
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draw: draw,
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wire: wire,
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tidy: tidy,
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examples: examples,
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doc-ref: doc-ref
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)
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)
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#tidy.show-module(electrical-docs, sort-functions: false)
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@ -1,2 +0,0 @@
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#import "elements/electrical/capacitor.typ": capacitor
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#import "elements/electrical/resistor.typ": resistor
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@ -11,8 +11,10 @@
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#import "elements/logic/or.typ": gate-or, gate-nor
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#import "elements/logic/xor.typ": gate-xor, gate-xnor
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#import "elements/logic/buf.typ": gate-buf, gate-not
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#import "elements/electrical/resistor.typ": resistor
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#import "elements/electrical/capacitor.typ": capacitor
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#import "elements/logic/iec_gate.typ": iec-gate
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#import "elements/logic/iec_and.typ": gate-iec-and, gate-iec-nand
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#import "elements/logic/iec_buf.typ": gate-iec-buf, gate-iec-not
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#import "elements/logic/iec_or.typ": gate-iec-or, gate-iec-nor
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#import "elements/logic/iec_xor.typ": gate-iec-xor, gate-iec-nxor
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#import "elements/group.typ": group
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@ -1,138 +0,0 @@
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#import "@preview/cetz:0.2.2": draw
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#import "../element.typ"
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#import "../ports.typ": add-port
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#let draw-shape(
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id, tl, tr, br, bl,
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fill, stroke,
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vertical: false,
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gap: 0.2,
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scales: (100%, 100%),
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symbols: (none, none)
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) = {
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let (x0, y0) = tl
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let (x1, y1) = br
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let w = x1 - x0
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let h = y1 - y0
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let (o0, s0) = if vertical {(y0, h)} else {(x0, w)}
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let (o1, s1) = if vertical {(x0, w)} else {(y0, h)}
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let m1 = o1 + s1 / 2
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let pt(i, j) = if vertical {
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(j, i)
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} else {
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(i, j)
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}
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let size0 = s1 * scales.first() / 100%
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let size1 = s1 * scales.last() / 100%
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if type(gap) == ratio {
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gap = gap / 100%
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} else {
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gap = gap / calc.abs(s0)
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}
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let r0 = 0.5 - gap / 2
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let r1 = 0.5 + gap / 2
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// Coordinates in (main axis, secondary axis) format
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let p0 = pt(o0, m1)
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let p1 = pt(o0 + r0 * s0, m1)
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let p2 = pt(o0 + r1 * s0, m1)
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let p3 = pt(o0 + s0, m1)
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let p4 = pt(o0 + r0 * s0, m1 - size0 / 2)
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let p5 = pt(o0 + r0 * s0, m1 + size0 / 2)
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let p6 = pt(o0 + r1 * s0, m1 - size1 / 2)
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let p7 = pt(o0 + r1 * s0, m1 + size1 / 2)
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let line = draw.line.with(stroke: stroke)
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let f = draw.group(name: id, {
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line(p0, p1)
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line(p2, p3)
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line(p4, p5)
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line(p6, p7)
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if symbols.first() != none {
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draw.content(
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p1,
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symbols.first(),
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anchor: if vertical {"south-west"} else {"south-east"},
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padding: 2pt
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||||
)
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||||
}
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||||
|
||||
if symbols.last() != none {
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draw.content(
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p2,
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symbols.last(),
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anchor: if vertical {"north-west"} else {"south-west"},
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padding: 2pt
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||||
)
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||||
}
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})
|
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return (f, tl, tr, br, bl)
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}
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|
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/// Draws a capacitor
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||||
///
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/// #examples.capacitor
|
||||
/// For other parameters description, see #doc-ref("element.elmt")
|
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/// - vertical (bool): Whether the element is vertical or horizontal.
|
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/// - If false, port 0 is placed on the west side and port 1 on the east.\
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/// - If true, they are on the north, respectively the south sides
|
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/// - gap (number, ratio): The gap between both sides
|
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/// - if it is a number (int or float), it is interpreted as an absolute canvas-unit length
|
||||
/// - if it is a ratio, it is interpreted as proportional to the capacitor's length (width if horizontal, height if vertical)
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/// - scales (array): A pair of ratios, the sizes of the sides relative to the capacitor's height (width if vertical).
|
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/// - symbols (array): A pair of content or strings (or none values) to attach on the sides of the capacitor
|
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#let capacitor(
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||||
x: none,
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y: none,
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w: none,
|
||||
h: none,
|
||||
name: none,
|
||||
name-anchor: "center",
|
||||
vertical: false,
|
||||
gap: 0.2,
|
||||
scales: (100%, 100%),
|
||||
symbols: (none, none),
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
debug: (
|
||||
ports: false
|
||||
)
|
||||
) = {
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||||
let ports = if vertical {(
|
||||
north: ((id: "0"),),
|
||||
south: ((id: "1"),)
|
||||
)} else {(
|
||||
west: ((id: "0"),),
|
||||
east: ((id: "1"),)
|
||||
)}
|
||||
|
||||
element.elmt(
|
||||
draw-shape: draw-shape.with(
|
||||
vertical: vertical,
|
||||
gap: gap,
|
||||
scales: scales,
|
||||
symbols: symbols
|
||||
),
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
name: name,
|
||||
name-anchor: name-anchor,
|
||||
ports: ports,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
debug: debug
|
||||
)
|
||||
}
|
||||
@ -1,106 +0,0 @@
|
||||
#import "@preview/cetz:0.2.2": draw
|
||||
#import "../element.typ"
|
||||
#import "../ports.typ": add-port
|
||||
|
||||
#let draw-shape(
|
||||
id, tl, tr, br, bl,
|
||||
fill, stroke,
|
||||
zigzags: 6,
|
||||
vertical: false
|
||||
) = {
|
||||
let (x0, y0) = tl
|
||||
let (x1, y1) = br
|
||||
|
||||
let w = x1 - x0
|
||||
let h = y1 - y0
|
||||
|
||||
let (o0, s0) = if vertical {(y0, h)} else {(x0, w)}
|
||||
let (o1, s1) = if vertical {(x0, w)} else {(y0, h)}
|
||||
let m1 = o1 + s1 / 2
|
||||
|
||||
let pt(i, j) = if vertical {
|
||||
(j, i)
|
||||
} else {
|
||||
(i, j)
|
||||
}
|
||||
|
||||
let p0 = pt(o0, m1)
|
||||
let p1 = pt(o0 + 0.2 * s0, m1)
|
||||
let p2 = pt(o0 + 0.8 * s0, m1)
|
||||
let p3 = pt(o0 + s0, m1)
|
||||
|
||||
if zigzags == none {
|
||||
let p4 = pt(o0 + 0.2 * s0, o1)
|
||||
let p5 = pt(o0 + 0.8 * s0, o1 + s1)
|
||||
let f = draw.group(name: id, {
|
||||
draw.line(p0, p1)
|
||||
draw.line(p2, p3)
|
||||
draw.rect(p4, p5, stroke: stroke, fill: fill)
|
||||
})
|
||||
return (f, tl, tr, br, bl)
|
||||
}
|
||||
|
||||
let pts = (p0, p1)
|
||||
|
||||
for i in range(zigzags) {
|
||||
let r = ((i+0.5) / zigzags * 0.6 + 0.2)
|
||||
let pos = pt(o0 + r * s0, o1 + s1 * calc.rem(i, 2))
|
||||
pts.push(pos)
|
||||
}
|
||||
|
||||
pts += (p2, p3)
|
||||
|
||||
let f = draw.group(name: id, {
|
||||
draw.line(..pts, stroke: stroke)
|
||||
})
|
||||
return (f, tl, tr, br, bl)
|
||||
}
|
||||
|
||||
/// Draws a resistor
|
||||
///
|
||||
/// #examples.resistor
|
||||
/// For other parameters description, see #doc-ref("element.elmt")
|
||||
/// - vertical (bool): Whether the element is vertical or horizontal. If false, port 0 is placed on the west side and port 1 on the east. If true, they are on the north, respectively the south sides
|
||||
/// - zigzags (number, none): Number of zigzags to draw. If none, a rectangle is drawn
|
||||
#let resistor(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
name: none,
|
||||
name-anchor: "center",
|
||||
vertical: false,
|
||||
zigzags: 6,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
debug: (
|
||||
ports: false
|
||||
)
|
||||
) = {
|
||||
let ports = if vertical {(
|
||||
north: ((id: "0"),),
|
||||
south: ((id: "1"),)
|
||||
)} else {(
|
||||
west: ((id: "0"),),
|
||||
east: ((id: "1"),)
|
||||
)}
|
||||
|
||||
element.elmt(
|
||||
draw-shape: draw-shape.with(
|
||||
vertical: vertical,
|
||||
zigzags: zigzags
|
||||
),
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
name: name,
|
||||
name-anchor: name-anchor,
|
||||
ports: ports,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
debug: debug
|
||||
)
|
||||
}
|
||||
70
src/elements/logic/iec_and.typ
Normal file
70
src/elements/logic/iec_and.typ
Normal file
@ -0,0 +1,70 @@
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
// #import "iec_gate.typ" as iec-gate
|
||||
#import "iec_gate.typ" as iec-gate
|
||||
|
||||
|
||||
/// Draws an IEC-AND gate. This function is also available as `element.iec-gate-and()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-and
|
||||
#let gate-iec-and(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false
|
||||
),
|
||||
) = {
|
||||
iec-gate.iec-gate(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: inverted,
|
||||
debug: debug,
|
||||
symbol: $amp$,
|
||||
)
|
||||
|
||||
}
|
||||
|
||||
/// Draws an IEC-NAND gate. This function is also available as `element.iec-gate-nand()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-nand
|
||||
#let gate-iec-nand(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false
|
||||
),
|
||||
) = {
|
||||
gate-iec-and(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
|
||||
debug: debug,
|
||||
)
|
||||
}
|
||||
68
src/elements/logic/iec_buf.typ
Normal file
68
src/elements/logic/iec_buf.typ
Normal file
@ -0,0 +1,68 @@
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
#import "iec_gate.typ" as iec-gate
|
||||
|
||||
|
||||
/// Draws an IEC buffer gate. This function is also available as `element.iec-gate-buf()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-buf
|
||||
#let gate-iec-buf(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false,
|
||||
),
|
||||
) = {
|
||||
iec-gate.iec-gate(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: inverted,
|
||||
debug: debug,
|
||||
symbol: "1",
|
||||
)
|
||||
}
|
||||
|
||||
/// Draws an IEC NOT gate. This function is also available as `element.iec-gate-not()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-not
|
||||
#let gate-iec-not(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false,
|
||||
),
|
||||
) = {
|
||||
gate-iec-buf(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: if inverted != "all" { inverted + ("out",) } else { inverted },
|
||||
debug: debug,
|
||||
)
|
||||
}
|
||||
148
src/elements/logic/iec_gate.typ
Normal file
148
src/elements/logic/iec_gate.typ
Normal file
@ -0,0 +1,148 @@
|
||||
#import "@preview/cetz:0.3.2": draw, coordinate
|
||||
#import "../ports.typ": add-ports, add-port
|
||||
#import "../element.typ"
|
||||
|
||||
#let default-draw-shape(id, tl, tr, br, bl, fill, stroke, symbol) = {
|
||||
let (x, y) = bl
|
||||
let (width, height) = (tr.at(0) - x, tr.at(1) - y)
|
||||
|
||||
let t = (x + width / 2, y + height)
|
||||
let b = (x + width / 2, y)
|
||||
|
||||
let f = draw.group(
|
||||
name: id,
|
||||
{
|
||||
draw.merge-path(
|
||||
inset: 0.5em,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
name: id + "-path",
|
||||
close: true,
|
||||
{
|
||||
draw.line(bl, tl, tr, br)
|
||||
},
|
||||
)
|
||||
|
||||
draw.content(
|
||||
(x + width / 2, y + height / 2),
|
||||
padding: 0.5em,
|
||||
align(center)[*$ symbol $*],
|
||||
)
|
||||
|
||||
draw.anchor("north", t)
|
||||
draw.anchor("south", b)
|
||||
},
|
||||
)
|
||||
return (f, tl, tr, br, bl)
|
||||
}
|
||||
|
||||
|
||||
/// Draws a logic gate. This function is also available as `element.iec-gate()`
|
||||
///
|
||||
/// - draw-shape (function): see #doc-ref("element.elmt")
|
||||
/// - x (number, dictionary): see #doc-ref("element.elmt")
|
||||
/// - y (number, dictionary): see #doc-ref("element.elmt")
|
||||
/// - w (number): see #doc-ref("element.elmt")
|
||||
/// - h (number): see #doc-ref("element.elmt")
|
||||
/// - inputs (int): The number of inputs
|
||||
/// - fill (none, color): see #doc-ref("element.elmt")
|
||||
/// - stroke (stroke): see #doc-ref("element.elmt")
|
||||
/// - id (str): see #doc-ref("element.elmt")
|
||||
/// - inverted (str, array): Either "all" or an array of port ids to display as inverted
|
||||
/// - inverted-radius (number): The radius of inverted ports dot
|
||||
/// - debug (dictionary): see #doc-ref("element.elmt")
|
||||
/// - symbol (str): The symbol to display at the center of the gate
|
||||
#let iec-gate(
|
||||
draw-shape: default-draw-shape,
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
inverted-radius: 0.1,
|
||||
debug: (
|
||||
ports: false
|
||||
),
|
||||
symbol: "",
|
||||
) = draw.get-ctx(ctx => {
|
||||
let width = w
|
||||
let height = h
|
||||
|
||||
let x = x
|
||||
let y = y
|
||||
if x == none { panic("Parameter x must be set") }
|
||||
if y == none { panic("Parameter y must be set") }
|
||||
if w == none { panic("Parameter w must be set") }
|
||||
if h == none { panic("Parameter h must be set") }
|
||||
|
||||
if (type(x) == dictionary) {
|
||||
let offset = x.rel
|
||||
let to = x.to
|
||||
let (ctx, to-pos) = coordinate.resolve(ctx, (rel: (offset, 0), to: to))
|
||||
x = to-pos.at(0)
|
||||
}
|
||||
|
||||
if (type(y) == dictionary) {
|
||||
let from = y.from
|
||||
let to = y.to
|
||||
|
||||
let dy
|
||||
if to == "out" {
|
||||
dy = height / 2
|
||||
} else {
|
||||
dy = height * (i + 0.5) / inputs
|
||||
}
|
||||
|
||||
let (ctx, from-pos) = coordinate.resolve(ctx, from)
|
||||
y = from-pos.at(1) + dy - height
|
||||
}
|
||||
|
||||
let tl = (x, y + height)
|
||||
let tr = (x + width, y + height)
|
||||
let br = (x + width, y)
|
||||
let bl = (x, y)
|
||||
|
||||
// Workaround because CeTZ needs to have all draw functions in the body
|
||||
let func = {}
|
||||
(func, tl, tr, br, bl) = draw-shape(id, tl, tr, br, bl, fill, stroke, symbol)
|
||||
func
|
||||
|
||||
let space = 100% / inputs
|
||||
for i in range(inputs) {
|
||||
let pct = (i + 0.5) * space
|
||||
let a = (tl, pct, bl)
|
||||
let b = (tr, pct, br)
|
||||
let int-name = id + "i" + str(i)
|
||||
draw.intersections(
|
||||
int-name,
|
||||
func,
|
||||
draw.hide(draw.line(a, b))
|
||||
)
|
||||
let port-name = "in" + str(i)
|
||||
let port-pos = int-name + ".0"
|
||||
if inverted == "all" or port-name in inverted {
|
||||
draw.circle(port-pos, radius: inverted-radius, anchor: "east", stroke: stroke)
|
||||
port-pos = (rel: (-2 * inverted-radius, 0), to: port-pos)
|
||||
}
|
||||
add-port(
|
||||
id, "west",
|
||||
(id: port-name), port-pos,
|
||||
debug: debug.ports
|
||||
)
|
||||
}
|
||||
|
||||
let out-pos = id + ".east"
|
||||
if inverted == "all" or "out" in inverted {
|
||||
draw.circle(out-pos, radius: inverted-radius, anchor: "west", stroke: stroke)
|
||||
out-pos = (rel: (2 * inverted-radius, 0), to: out-pos)
|
||||
}
|
||||
add-port(
|
||||
id, "east",
|
||||
(id: "out"), out-pos,
|
||||
debug: debug.ports
|
||||
)
|
||||
})
|
||||
67
src/elements/logic/iec_or.typ
Normal file
67
src/elements/logic/iec_or.typ
Normal file
@ -0,0 +1,67 @@
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
#import "iec_gate.typ" as iec-gate
|
||||
|
||||
/// Draws an IEC-OR gate. This function is also available as `element.iec-gate-or()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-or
|
||||
#let gate-iec-or(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false
|
||||
)
|
||||
) = {
|
||||
iec-gate.iec-gate(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: inverted,
|
||||
debug: debug,
|
||||
symbol: $>= 1$,
|
||||
)
|
||||
}
|
||||
|
||||
/// Draws an IEC-NOR gate. This function is also available as `element.iec-gate-nor()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-nor
|
||||
#let gate-iec-nor(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false
|
||||
)
|
||||
) = {
|
||||
gate-iec-or(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
|
||||
debug: debug
|
||||
)
|
||||
}
|
||||
67
src/elements/logic/iec_xor.typ
Normal file
67
src/elements/logic/iec_xor.typ
Normal file
@ -0,0 +1,67 @@
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
#import "iec_gate.typ" as iec-gate
|
||||
|
||||
/// Draws an IEC-XOR gate. This function is also available as `element.iec-gate-xor()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-xor
|
||||
#let gate-iec-xor(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false
|
||||
)
|
||||
) = {
|
||||
iec-gate.iec-gate(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: inverted,
|
||||
debug: debug,
|
||||
symbol: $= 1$,
|
||||
)
|
||||
}
|
||||
|
||||
/// Draws an IEC-NXOR gate. This function is also available as `element.iec-gate-nxor()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-nxor
|
||||
#let gate-iec-nxor(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false
|
||||
)
|
||||
) = {
|
||||
gate-iec-xor(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
|
||||
debug: debug
|
||||
)
|
||||
}
|
||||
@ -3,3 +3,8 @@
|
||||
#import "elements/logic/or.typ": gate-or, gate-nor
|
||||
#import "elements/logic/xor.typ": gate-xor, gate-xnor
|
||||
#import "elements/logic/buf.typ": gate-buf, gate-not
|
||||
#import "elements/logic/iec_gate.typ": iec-gate
|
||||
#import "elements/logic/iec_and.typ": gate-iec-and, gate-iec-nand
|
||||
#import "elements/logic/iec_or.typ": gate-iec-or, gate-iec-nor
|
||||
#import "elements/logic/iec_buf.typ": gate-iec-buf, gate-iec-not
|
||||
#import "elements/logic/iec_xor.typ": gate-iec-xor, gate-iec-nxor
|
||||
|
||||
@ -1,7 +1,6 @@
|
||||
#let version = version(0, 2, 0)
|
||||
|
||||
#import "circuit.typ": circuit
|
||||
#import "electrical.typ"
|
||||
#import "element.typ"
|
||||
#import "gates.typ"
|
||||
#import "util.typ"
|
||||
|
||||
Reference in New Issue
Block a user