Compare commits
7 Commits
v0.1.0
...
add_iec_ga
Author | SHA1 | Date | |
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9966656e8b | |||
3ccb79c6c2 | |||
2bb7e3b5a9 | |||
371caf094c
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841f53e76c | |||
ff0b91e683
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e1e561bb6c
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@ -56,7 +56,7 @@ For more information, see the [manual](manual.pdf)
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To use this package, simply import [circuiteria](https://typst.app/universe/package/circuiteria) and call the `circuit` function:
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```typ
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#import "@preview/circuiteria:0.1.0"
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#import "@preview/circuiteria:0.2.0"
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#circuiteria.circuit({
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import circuiteria: *
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...
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@ -1,4 +1,4 @@
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#import "@preview/cetz:0.2.2": draw
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#import "@preview/cetz:0.3.2": draw
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#import "../src/circuit.typ": circuit
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#import "../src/util.typ"
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40
gallery.bash
@ -1,40 +0,0 @@
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#!/bin/bash
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PDFS=false
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while getopts "p" flag
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do
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case "${flag}" in
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p) PDFS=true;;
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esac
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done
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echo "Generating gallery images"
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set -- ./gallery/*.typ
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cnt="$#"
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i=1
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for f
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do
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f2="${f/typ/png}"
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echo "($i/$cnt) $f -> $f2"
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typst c --root ./ "$f" "$f2"
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i=$((i+1))
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done
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if [ "$PDFS" = true ]
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then
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echo
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echo "Generating gallery PDFs"
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set -- ./gallery/*.typ
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cnt="$#"
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i=1
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for f
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do
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f2="${f/typ/pdf}"
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echo "($i/$cnt) $f -> $f2"
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typst c --root ./ "$f" "$f2"
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i=$((i+1))
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done
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fi
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Before Width: | Height: | Size: 45 KiB After Width: | Height: | Size: 45 KiB |
BIN
gallery/test.png
Before Width: | Height: | Size: 142 KiB After Width: | Height: | Size: 142 KiB |
Before Width: | Height: | Size: 142 KiB After Width: | Height: | Size: 142 KiB |
Before Width: | Height: | Size: 66 KiB After Width: | Height: | Size: 66 KiB |
@ -1,4 +1,4 @@
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#import "@preview/cetz:0.2.2": draw
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#import "@preview/cetz:0.3.2": draw
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#import "../src/lib.typ": circuit, element, util, wire
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#set page(width: auto, height: auto, margin: .5cm)
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|
Before Width: | Height: | Size: 159 KiB After Width: | Height: | Size: 159 KiB |
@ -1,4 +1,4 @@
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#import "@preview/cetz:0.2.2": draw
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#import "@preview/cetz:0.3.2": draw
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#import "../src/lib.typ": *
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#set page(width: auto, height: auto, margin: .5cm)
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Before Width: | Height: | Size: 276 KiB After Width: | Height: | Size: 275 KiB |
@ -1,4 +1,4 @@
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#import "@preview/cetz:0.2.2": draw
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#import "@preview/cetz:0.3.2": draw
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#import "../src/lib.typ": *
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#set page(width: auto, height: auto, margin: .5cm)
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|
Before Width: | Height: | Size: 76 KiB After Width: | Height: | Size: 76 KiB |
@ -1,4 +1,4 @@
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#import "@preview/cetz:0.2.2": draw, vector
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#import "@preview/cetz:0.3.2": draw, vector
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#import "../src/lib.typ": *
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#set page(width: auto, height: auto, margin: .5cm)
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|
BIN
gallery/test7.pdf
Normal file
BIN
gallery/test7.png
Normal file
After Width: | Height: | Size: 34 KiB |
98
gallery/test7.typ
Normal file
@ -0,0 +1,98 @@
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#import "@preview/cetz:0.3.2": draw
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#import "../src/lib.typ": circuit, element, util, wire
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#set page(width: auto, height: auto, margin: .5cm)
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#circuit({
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element.gate-iec-buf(
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x: 0,
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y: 0,
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w: 2,
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h: 2,
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id: "iec-buf",
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inputs: 1,
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)
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wire.stub("iec-buf-port-in0", "west")
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element.gate-iec-not(
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x: 3,
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y: 0,
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w: 2,
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h: 2,
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id: "iec-not",
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inputs: 1,
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)
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wire.stub("iec-not-port-in0", "west")
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element.gate-iec-and(
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id: "iec-and",
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x: 0,
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y: -3,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-and-port-in" + str(i), "west")
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}
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element.gate-iec-nand(
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id: "iec-nand",
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x: 3,
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y: -3,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-nand-port-in" + str(i), "west")
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}
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element.gate-iec-or(
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id: "iec-or",
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x: 0,
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y: -6,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-or-port-in" + str(i), "west")
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}
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element.gate-iec-nor(
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id: "iec-nor",
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x: 3,
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y: -6,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-nor-port-in" + str(i), "west")
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}
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element.gate-iec-xor(
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id: "iec-xor",
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x: 0,
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y: -9,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-xor-port-in" + str(i), "west")
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}
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element.gate-iec-nxor(
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id: "iec-nxor",
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x: 3,
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y: -9,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-nxor-port-in" + str(i), "west")
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}
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})
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11
justfile
Normal file
@ -0,0 +1,11 @@
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# Local Variables:
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# mode: makefile
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# End:
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gallery_dir := "./gallery"
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set shell := ["bash", "-uc"]
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manual:
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typst c manual.typ manual.pdf
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gallery:
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for f in "{{gallery_dir}}"/*.typ; do typst c --root . "$f" "${f%typ}png"; done
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BIN
manual.pdf
41
manual.typ
@ -1,5 +1,5 @@
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#import "@preview/tidy:0.3.0"
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#import "@preview/cetz:0.2.2": draw, canvas
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#import "@preview/tidy:0.4.1"
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#import "@preview/cetz:0.3.2": draw, canvas
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#import "src/lib.typ"
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#import "doc/examples.typ"
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#import "src/circuit.typ": circuit
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@ -12,7 +12,7 @@
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numbering("1.1", ..num)
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})
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#{
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outline(indent: true, depth: 3)
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outline(indent: auto, depth: 3)
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}
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#show link: set text(blue)
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@ -47,7 +47,7 @@
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#set page(numbering: "1/1", header: align(right)[circuiteria #sym.dash.em v#lib.version])
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#set page(
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header: locate(loc => {
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header: context {
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let txt = [circuiteria #sym.dash.em v#lib.version]
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let cnt = counter(heading)
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let cnt-val = cnt.get()
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@ -65,8 +65,8 @@
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#rect(width: 100%, height: .5em, radius: .25em, stroke: none, fill: util.colors.values().at(i))
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]
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)
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}),
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footer: locate(loc => {
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},
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footer: context {
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let cnt = counter(heading)
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let cnt-val = cnt.get()
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if cnt-val.len() < 2 { return }
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@ -80,12 +80,12 @@
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],
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counter(page).display("1/1", both: true)
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)
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})
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}
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)
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#let doc-ref(target, full: false, var: false) = {
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let (module, func) = target.split(".")
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let label-name = module + func
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let label-name = module + "-" + func
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let display-name = func
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if full {
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display-name = target
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@ -94,7 +94,7 @@
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label-name += "()"
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display-name += "()"
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}
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link(label(label-name))[#display-name]
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link(label(label-name), raw(display-name))
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}
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= Introduction
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@ -103,11 +103,21 @@ This package provides a way to make beautiful block circuit diagrams using the C
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= Usage
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Simply import #link("src/lib.typ") and call the `circuit` function:
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Simply import Circuiteria and call the `circuit` function:
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#pad(left: 1em)[```typ
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#import "src/lib.typ"
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#lib.circuit({
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import lib: *
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#import "@preview/circuiteria:0.2.0"
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#circuiteria.circuit({
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import circuiteria: *
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...
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})
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```]
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== Project installation
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If you have installed Circuiteria directly in your project, import #link("src/lib.typ") and call the `circuit` function:
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#pad(left: 1em)[```typ
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#import "src/lib.typ" as circuiteria
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#circuiteria.circuit({
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import circuiteria: *
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...
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})
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```]
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@ -117,6 +127,7 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
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#let circuit-docs = tidy.parse-module(
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read("src/circuit.typ"),
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name: "circuit",
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old-syntax: true,
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require-all-parameters: true
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)
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#tidy.show-module(circuit-docs)
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@ -126,6 +137,7 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
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#let util-docs = tidy.parse-module(
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read("src/util.typ"),
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name: "util",
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old-syntax: true,
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require-all-parameters: true,
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scope: (
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util: util,
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@ -140,6 +152,7 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
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#let wire-docs = tidy.parse-module(
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read("src/wire.typ"),
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name: "wire",
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old-syntax: true,
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require-all-parameters: true,
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scope: (
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wire: wire,
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@ -161,6 +174,7 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
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read("src/elements/multiplexer.typ") + "\n" +
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read("src/elements/group.typ"),
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name: "element",
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old-syntax: true,
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scope: (
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element: element,
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circuit: circuit,
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@ -183,6 +197,7 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
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read("src/elements/logic/or.typ") + "\n" +
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read("src/elements/logic/xor.typ"),
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name: "gates",
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old-syntax: true,
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scope: (
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element: element,
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circuit: circuit,
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|
@ -1,4 +1,4 @@
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#import "@preview/cetz:0.2.2": canvas
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#import "@preview/cetz:0.3.2": canvas
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#import "@preview/tidy:0.3.0"
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/// Draws a block circuit diagram
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|
@ -11,5 +11,10 @@
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#import "elements/logic/or.typ": gate-or, gate-nor
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#import "elements/logic/xor.typ": gate-xor, gate-xnor
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#import "elements/logic/buf.typ": gate-buf, gate-not
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#import "elements/logic/iec_gate.typ": iec-gate
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#import "elements/logic/iec_and.typ": gate-iec-and, gate-iec-nand
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#import "elements/logic/iec_buf.typ": gate-iec-buf, gate-iec-not
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#import "elements/logic/iec_or.typ": gate-iec-or, gate-iec-nor
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#import "elements/logic/iec_xor.typ": gate-iec-xor, gate-iec-nxor
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#import "elements/group.typ": group
|
@ -1,4 +1,4 @@
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#import "@preview/cetz:0.2.2": draw
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#import "@preview/cetz:0.3.2": draw
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#import "element.typ"
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#import "ports.typ": add-port
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|
@ -1,4 +1,4 @@
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#import "@preview/cetz:0.2.2": draw
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#import "@preview/cetz:0.3.2": draw
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#import "element.typ"
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#let draw-shape(id, tl, tr, br, bl, fill, stroke) = {
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|
@ -1,4 +1,4 @@
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#import "@preview/cetz:0.2.2": draw, coordinate
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#import "@preview/cetz:0.3.2": draw, coordinate
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#import "ports.typ": add-ports, add-port
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#import "../util.typ"
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@ -88,16 +88,27 @@
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if to-side in ports-margins {
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margins = ports-margins.at(to-side)
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}
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let dy
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let top-margin
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if to-side in ("east", "west") {
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let used-pct = 100% - margins.at(0) - margins.at(1)
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let used-height = height * used-pct / 100%
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let top-margin = height * margins.at(0) / 100%
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top-margin = height * margins.at(0) / 100%
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let dy = used-height * (i + 1) / (ports.at(to-side).len() + 1)
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dy = used-height * (i + 1) / (ports.at(to-side).len() + 1)
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if not auto-ports {
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top-margin = 0
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dy = ports-y.at(to)(height)
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}
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} else if to-side == "north" {
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dy = 0
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top-margin = 0
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} else if to-side == "south" {
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dy = height
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top-margin = 0
|
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}
|
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|
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let (ctx, from-pos) = coordinate.resolve(ctx, from)
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y = from-pos.at(1) + dy - height + top-margin
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||||
|
@ -1,4 +1,4 @@
|
||||
#import "@preview/cetz:0.2.2": draw
|
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#import "@preview/cetz:0.3.2": draw
|
||||
#import "element.typ"
|
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#import "ports.typ": add-port
|
||||
|
||||
|
@ -1,4 +1,4 @@
|
||||
#import "@preview/cetz:0.2.2": draw, coordinate
|
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#import "@preview/cetz:0.3.2": draw, coordinate
|
||||
#import "../util.typ"
|
||||
|
||||
/// Draws a group of elements
|
||||
|
@ -1,4 +1,4 @@
|
||||
#import "@preview/cetz:0.2.2": draw
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
#import "gate.typ"
|
||||
|
||||
#let draw-shape(id, tl, tr, br, bl, fill, stroke) = {
|
||||
|
@ -1,4 +1,4 @@
|
||||
#import "@preview/cetz:0.2.2": draw
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
#import "gate.typ"
|
||||
|
||||
#let draw-shape(id, tl, tr, br, bl, fill, stroke) = {
|
||||
|
@ -1,4 +1,4 @@
|
||||
#import "@preview/cetz:0.2.2": draw, coordinate
|
||||
#import "@preview/cetz:0.3.2": draw, coordinate
|
||||
#import "../ports.typ": add-ports, add-port
|
||||
#import "../element.typ"
|
||||
|
||||
|
70
src/elements/logic/iec_and.typ
Normal file
@ -0,0 +1,70 @@
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
// #import "iec_gate.typ" as iec-gate
|
||||
#import "iec_gate.typ" as iec-gate
|
||||
|
||||
|
||||
/// Draws an IEC-AND gate. This function is also available as `element.iec-gate-and()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-and
|
||||
#let gate-iec-and(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false
|
||||
),
|
||||
) = {
|
||||
iec-gate.iec-gate(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: inverted,
|
||||
debug: debug,
|
||||
symbol: $amp$,
|
||||
)
|
||||
|
||||
}
|
||||
|
||||
/// Draws an IEC-NAND gate. This function is also available as `element.iec-gate-nand()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-nand
|
||||
#let gate-iec-nand(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false
|
||||
),
|
||||
) = {
|
||||
gate-iec-and(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
|
||||
debug: debug,
|
||||
)
|
||||
}
|
68
src/elements/logic/iec_buf.typ
Normal file
@ -0,0 +1,68 @@
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
#import "iec_gate.typ" as iec-gate
|
||||
|
||||
|
||||
/// Draws an IEC buffer gate. This function is also available as `element.iec-gate-buf()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-buf
|
||||
#let gate-iec-buf(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false,
|
||||
),
|
||||
) = {
|
||||
iec-gate.iec-gate(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: inverted,
|
||||
debug: debug,
|
||||
symbol: "1",
|
||||
)
|
||||
}
|
||||
|
||||
/// Draws an IEC NOT gate. This function is also available as `element.iec-gate-not()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-not
|
||||
#let gate-iec-not(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false,
|
||||
),
|
||||
) = {
|
||||
gate-iec-buf(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: if inverted != "all" { inverted + ("out",) } else { inverted },
|
||||
debug: debug,
|
||||
)
|
||||
}
|
148
src/elements/logic/iec_gate.typ
Normal file
@ -0,0 +1,148 @@
|
||||
#import "@preview/cetz:0.3.2": draw, coordinate
|
||||
#import "../ports.typ": add-ports, add-port
|
||||
#import "../element.typ"
|
||||
|
||||
#let default-draw-shape(id, tl, tr, br, bl, fill, stroke, symbol) = {
|
||||
let (x, y) = bl
|
||||
let (width, height) = (tr.at(0) - x, tr.at(1) - y)
|
||||
|
||||
let t = (x + width / 2, y + height)
|
||||
let b = (x + width / 2, y)
|
||||
|
||||
let f = draw.group(
|
||||
name: id,
|
||||
{
|
||||
draw.merge-path(
|
||||
inset: 0.5em,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
name: id + "-path",
|
||||
close: true,
|
||||
{
|
||||
draw.line(bl, tl, tr, br)
|
||||
},
|
||||
)
|
||||
|
||||
draw.content(
|
||||
(x + width / 2, y + height / 2),
|
||||
padding: 0.5em,
|
||||
align(center)[*$ symbol $*],
|
||||
)
|
||||
|
||||
draw.anchor("north", t)
|
||||
draw.anchor("south", b)
|
||||
},
|
||||
)
|
||||
return (f, tl, tr, br, bl)
|
||||
}
|
||||
|
||||
|
||||
/// Draws a logic gate. This function is also available as `element.iec-gate()`
|
||||
///
|
||||
/// - draw-shape (function): see #doc-ref("element.elmt")
|
||||
/// - x (number, dictionary): see #doc-ref("element.elmt")
|
||||
/// - y (number, dictionary): see #doc-ref("element.elmt")
|
||||
/// - w (number): see #doc-ref("element.elmt")
|
||||
/// - h (number): see #doc-ref("element.elmt")
|
||||
/// - inputs (int): The number of inputs
|
||||
/// - fill (none, color): see #doc-ref("element.elmt")
|
||||
/// - stroke (stroke): see #doc-ref("element.elmt")
|
||||
/// - id (str): see #doc-ref("element.elmt")
|
||||
/// - inverted (str, array): Either "all" or an array of port ids to display as inverted
|
||||
/// - inverted-radius (number): The radius of inverted ports dot
|
||||
/// - debug (dictionary): see #doc-ref("element.elmt")
|
||||
/// - symbol (str): The symbol to display at the center of the gate
|
||||
#let iec-gate(
|
||||
draw-shape: default-draw-shape,
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
inverted-radius: 0.1,
|
||||
debug: (
|
||||
ports: false
|
||||
),
|
||||
symbol: "",
|
||||
) = draw.get-ctx(ctx => {
|
||||
let width = w
|
||||
let height = h
|
||||
|
||||
let x = x
|
||||
let y = y
|
||||
if x == none { panic("Parameter x must be set") }
|
||||
if y == none { panic("Parameter y must be set") }
|
||||
if w == none { panic("Parameter w must be set") }
|
||||
if h == none { panic("Parameter h must be set") }
|
||||
|
||||
if (type(x) == dictionary) {
|
||||
let offset = x.rel
|
||||
let to = x.to
|
||||
let (ctx, to-pos) = coordinate.resolve(ctx, (rel: (offset, 0), to: to))
|
||||
x = to-pos.at(0)
|
||||
}
|
||||
|
||||
if (type(y) == dictionary) {
|
||||
let from = y.from
|
||||
let to = y.to
|
||||
|
||||
let dy
|
||||
if to == "out" {
|
||||
dy = height / 2
|
||||
} else {
|
||||
dy = height * (i + 0.5) / inputs
|
||||
}
|
||||
|
||||
let (ctx, from-pos) = coordinate.resolve(ctx, from)
|
||||
y = from-pos.at(1) + dy - height
|
||||
}
|
||||
|
||||
let tl = (x, y + height)
|
||||
let tr = (x + width, y + height)
|
||||
let br = (x + width, y)
|
||||
let bl = (x, y)
|
||||
|
||||
// Workaround because CeTZ needs to have all draw functions in the body
|
||||
let func = {}
|
||||
(func, tl, tr, br, bl) = draw-shape(id, tl, tr, br, bl, fill, stroke, symbol)
|
||||
func
|
||||
|
||||
let space = 100% / inputs
|
||||
for i in range(inputs) {
|
||||
let pct = (i + 0.5) * space
|
||||
let a = (tl, pct, bl)
|
||||
let b = (tr, pct, br)
|
||||
let int-name = id + "i" + str(i)
|
||||
draw.intersections(
|
||||
int-name,
|
||||
func,
|
||||
draw.hide(draw.line(a, b))
|
||||
)
|
||||
let port-name = "in" + str(i)
|
||||
let port-pos = int-name + ".0"
|
||||
if inverted == "all" or port-name in inverted {
|
||||
draw.circle(port-pos, radius: inverted-radius, anchor: "east", stroke: stroke)
|
||||
port-pos = (rel: (-2 * inverted-radius, 0), to: port-pos)
|
||||
}
|
||||
add-port(
|
||||
id, "west",
|
||||
(id: port-name), port-pos,
|
||||
debug: debug.ports
|
||||
)
|
||||
}
|
||||
|
||||
let out-pos = id + ".east"
|
||||
if inverted == "all" or "out" in inverted {
|
||||
draw.circle(out-pos, radius: inverted-radius, anchor: "west", stroke: stroke)
|
||||
out-pos = (rel: (2 * inverted-radius, 0), to: out-pos)
|
||||
}
|
||||
add-port(
|
||||
id, "east",
|
||||
(id: "out"), out-pos,
|
||||
debug: debug.ports
|
||||
)
|
||||
})
|
67
src/elements/logic/iec_or.typ
Normal file
@ -0,0 +1,67 @@
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
#import "iec_gate.typ" as iec-gate
|
||||
|
||||
/// Draws an IEC-OR gate. This function is also available as `element.iec-gate-or()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-or
|
||||
#let gate-iec-or(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false
|
||||
)
|
||||
) = {
|
||||
iec-gate.iec-gate(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: inverted,
|
||||
debug: debug,
|
||||
symbol: $>= 1$,
|
||||
)
|
||||
}
|
||||
|
||||
/// Draws an IEC-NOR gate. This function is also available as `element.iec-gate-nor()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-nor
|
||||
#let gate-iec-nor(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false
|
||||
)
|
||||
) = {
|
||||
gate-iec-or(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
|
||||
debug: debug
|
||||
)
|
||||
}
|
67
src/elements/logic/iec_xor.typ
Normal file
@ -0,0 +1,67 @@
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
#import "iec_gate.typ" as iec-gate
|
||||
|
||||
/// Draws an IEC-XOR gate. This function is also available as `element.iec-gate-xor()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-xor
|
||||
#let gate-iec-xor(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false
|
||||
)
|
||||
) = {
|
||||
iec-gate.iec-gate(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: inverted,
|
||||
debug: debug,
|
||||
symbol: $= 1$,
|
||||
)
|
||||
}
|
||||
|
||||
/// Draws an IEC-NXOR gate. This function is also available as `element.iec-gate-nxor()`
|
||||
///
|
||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
||||
/// #examples.gate-iec-nxor
|
||||
#let gate-iec-nxor(
|
||||
x: none,
|
||||
y: none,
|
||||
w: none,
|
||||
h: none,
|
||||
inputs: 2,
|
||||
fill: none,
|
||||
stroke: black + 1pt,
|
||||
id: "",
|
||||
inverted: (),
|
||||
debug: (
|
||||
ports: false
|
||||
)
|
||||
) = {
|
||||
gate-iec-xor(
|
||||
x: x,
|
||||
y: y,
|
||||
w: w,
|
||||
h: h,
|
||||
inputs: inputs,
|
||||
fill: fill,
|
||||
stroke: stroke,
|
||||
id: id,
|
||||
inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
|
||||
debug: debug
|
||||
)
|
||||
}
|
@ -1,4 +1,4 @@
|
||||
#import "@preview/cetz:0.2.2": draw
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
#import "gate.typ"
|
||||
|
||||
#let draw-shape(id, tl, tr, br, bl, fill, stroke) = {
|
||||
|
@ -1,4 +1,4 @@
|
||||
#import "@preview/cetz:0.2.2": draw
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
#import "gate.typ"
|
||||
|
||||
#let space = 10%
|
||||
|
@ -1,4 +1,4 @@
|
||||
#import "@preview/cetz:0.2.2": draw
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
#import "../util.typ"
|
||||
#import "element.typ"
|
||||
#import "ports.typ": add-port
|
||||
|
@ -1,4 +1,4 @@
|
||||
#import "@preview/cetz:0.2.2": draw
|
||||
#import "@preview/cetz:0.3.2": draw
|
||||
#import "../util.typ": rotate-anchor
|
||||
|
||||
#let add-port(
|
||||
|
@ -3,3 +3,8 @@
|
||||
#import "elements/logic/or.typ": gate-or, gate-nor
|
||||
#import "elements/logic/xor.typ": gate-xor, gate-xnor
|
||||
#import "elements/logic/buf.typ": gate-buf, gate-not
|
||||
#import "elements/logic/iec_gate.typ": iec-gate
|
||||
#import "elements/logic/iec_and.typ": gate-iec-and, gate-iec-nand
|
||||
#import "elements/logic/iec_or.typ": gate-iec-or, gate-iec-nor
|
||||
#import "elements/logic/iec_buf.typ": gate-iec-buf, gate-iec-not
|
||||
#import "elements/logic/iec_xor.typ": gate-iec-xor, gate-iec-nxor
|
||||
|
@ -1,4 +1,4 @@
|
||||
#let version = version(0, 1, 0)
|
||||
#let version = version(0, 2, 0)
|
||||
|
||||
#import "circuit.typ": circuit
|
||||
#import "element.typ"
|
||||
|
@ -1,4 +1,4 @@
|
||||
#import "@preview/cetz:0.2.2": draw, coordinate
|
||||
#import "@preview/cetz:0.3.2": draw, coordinate
|
||||
#import "util.typ": opposite-anchor
|
||||
|
||||
/// List of valid wire styles
|
||||
|
@ -1,7 +1,7 @@
|
||||
[package]
|
||||
name = "circuiteria"
|
||||
version = "0.1.0"
|
||||
compiler = "0.11.0"
|
||||
version = "0.2.0"
|
||||
compiler = "0.13.0"
|
||||
repository = "https://git.kb28.ch/HEL/circuiteria"
|
||||
entrypoint = "src/lib.typ"
|
||||
authors = [
|
||||
@ -11,4 +11,4 @@ categories = [ "visualization" ]
|
||||
license = "Apache-2.0"
|
||||
description = "Drawing block circuits with Typst made easy, using CeTZ"
|
||||
keywords = [ "circuit", "block", "draw" ]
|
||||
exclude = [ "gallery", "gallery.bash", "doc" ]
|
||||
exclude = [ "gallery", "justfile", "doc" ]
|