forked from HEL/circuiteria
purpl3F0x
0c1272e35e
- Introduced `verilog.typ` for parsing Verilog/SystemVerilog source code, supporting both ANSI and non-ANSI port styles. - Implemented functions to analyze modules, infer AXI4, AXI4-Lite, and AXI4-Stream buses, as well as clock and reset signals. - Added rendering capabilities for Verilog modules, allowing for visual representation of ports and buses. - Created a new `gallery/verilog.typ` file to facilitate the drawing of Verilog blocks in diagrams. Signed-off-by: Stavros Avramidis <stavros9899@gmail.com>
13 lines
245 B
Typst
13 lines
245 B
Typst
#import "/src/lib.typ" as circuiteria: circuit, util, verilog
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#set page(width: auto, height: auto, margin: .5cm)
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#circuit({
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verilog.block(
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read("axi_demo.v"),
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x: 0, y: 0,
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// fill: util.colors.yellow,
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// radius: 0.05em
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)
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})
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