purpl3F0xandClaude Opus 5.5 6b861553b7 Pack and center Verilog block ports with automatic spacing ...

- Add `ports-align` ("center" by default, "top", "bottom", or "spread" for
  the previous evenly spread layout) and `ports-pitch` to `verilog.block`.
- Packed layouts use minimal margins, only reserving room for the module
  name and north/south ports, and size the block to the busiest side.
- The automatic height now also adapts to custom `ports-margins`.
- Regenerate the gallery image and the manual.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Signed-off-by: Stavros Avramidis <stavros9899@gmail.com>

2026-11-03 13:31:07 +02:00

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