Pull Requests - circuiteria - HERDAC

HEL/circuiteria

Labels Milestones New Pull Request

fix: handle y port alignment with gates

#22 by HEL was merged 2026-06-30 19:08:48 +00:00

fix/15-gate-y-port-alignment

Update manual and gallery documentation

#21 by HEL was merged 2026-06-30 17:18:26 +00:00

feat/update-manual-and-gallery

Update CeTZ

#20 by HEL was merged 2026-06-30 16:54:30 +00:00

feat/18-update-cetz

chore: expose package name

#19 by HEL was merged 2026-06-30 16:34:28 +00:00

feat/17-expose-name

feature: added guided wire style enhancement

#14 by Shmerlard was merged 2025-08-24 11:01:02 +00:00

1 approval

Add radius parameter to block enhancement

#12 by Shmerlard was merged 2025-08-17 12:36:04 +00:00

1 approval

feature: add IEC gates new component

#11 by bono was merged 2025-06-29 13:19:57 +00:00

bono:add_iec_gates

1 approval

v0.2.0: Updates

#5 by HEL was merged 2025-03-01 21:28:24 +00:00

updated compiler version + dependencies

#4 by HEL was merged 2025-03-01 21:17:27 +00:00