added riscv examples
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60
gallery/riscv/alu_instr.yaml
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60
gallery/riscv/alu_instr.yaml
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structures:
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main:
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bits: 32
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ranges:
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31-20:
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name: op2
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depends-on: 5
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values:
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0:
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description: second operand is an immediate value
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structure: immediateOp
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1:
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description: second operand is a register
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structure: registerOp
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19-15:
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name: rs1
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14-12:
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name: funct3
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description: operation
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values:
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000: add / sub
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100: xor
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110: or
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111: and
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001: sl
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101: sr
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11-7:
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name: rd
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6:
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name: 0
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5:
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name: I
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4:
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name: 1
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3:
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name: 0
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2:
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name: 0
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1:
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name: 1
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0:
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name: 1
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immediateOp:
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bits: 12
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ranges:
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11-0:
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name: 12-bit immediate value
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description: signed number
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registerOp:
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bits: 12
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ranges:
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11-5:
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name: funct7
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description: function modifier
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values:
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0000000: default (add, srl)
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"0100000": sub, sra
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4-0:
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name: rs2
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description: second register operand
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34
gallery/riscv/branch_instr.yaml
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34
gallery/riscv/branch_instr.yaml
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structures:
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main:
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bits: 32
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ranges:
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31-25:
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name: imm
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24-20:
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name: rs2
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19-15:
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name: rs1
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14-12:
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name: funct3
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description: function modifier
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values:
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000: if equal
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001: if not equal
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100: if less
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101: if greater or equal
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11-7:
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name: imm
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6:
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name: 1
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5:
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name: 1
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4:
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name: 0
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3:
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name: 0
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2:
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name: 0
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1:
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name: 1
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0:
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name: 1
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78
gallery/riscv/mem_instr.yaml
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78
gallery/riscv/mem_instr.yaml
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structures:
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main:
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bits: 32
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ranges:
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31-20:
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name: src
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depends-on: 5
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values:
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0:
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description:
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structure: srcImmediate
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1:
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description:
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structure: srcRegister
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19-15:
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name: rs1
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14-12:
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name: funct3
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description: function modifier
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values:
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000: byte
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001: half-word
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"010": word
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100: upper byte (load only)
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101: upper half (load only)
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11-7:
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name: dst
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depends-on: 5
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values:
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0:
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description:
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structure: dstRegister
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1:
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description:
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structure: dstImmediate
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6:
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name: 0
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5:
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name: I
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4:
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name: 0
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3:
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name: 0
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2:
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name: 0
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1:
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name: 1
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0:
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name: 1
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srcImmediate:
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bits: 12
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ranges:
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11-0:
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name: src
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description: source memory address
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srcRegister:
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bits: 12
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ranges:
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11-5:
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name: dstU
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description: destination address upper bits
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4-0:
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name: rs2
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description: source register
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dstImmediate:
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bits: 5
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ranges:
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4-0:
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name: destL
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description: destination address lower bits
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dstRegister:
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bits: 5
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ranges:
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4-0:
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name: rd
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description: destination register
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BIN
gallery/riscv/riscv.pdf
Normal file
BIN
gallery/riscv/riscv.pdf
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Binary file not shown.
14
gallery/riscv/riscv.typ
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14
gallery/riscv/riscv.typ
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#import "../../src/lib.typ": *
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#let conf = config.config(
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full-page: true,
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left-labels: true
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)
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#let alu = schema.load("/gallery/riscv/alu_instr.yaml")
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#schema.render(alu, config: conf)
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#let branch = schema.load("/gallery/riscv/branch_instr.yaml")
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#schema.render(branch, config: conf)
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#let mem = schema.load("/gallery/riscv/mem_instr.yaml")
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#schema.render(mem, config: conf)
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BIN
gallery/test.pdf
BIN
gallery/test.pdf
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@ -410,7 +410,6 @@
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shapes += draw-text(range_.name, txt-col, name-x, name-y, fill: bg-col)
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if range_.description != "" {
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//draw.circle((desc-x, -desc-y), radius: 5, fill: red)
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let shapes_
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(shapes_, desc-x, desc-y) = draw-description(
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config, range_, start-x, bits-y, width, desc-x, desc-y
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