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added riscv examples

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This commit is contained in:
Louis Heredero 2024-05-19 13:54:49 +02:00
parent 5e0e680f60
commit 44fd298edb
Signed by: HEL
GPG Key ID: 8D83DE470F8544E7
7 changed files with 186 additions and 1 deletions
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60
gallery/riscv/alu_instr.yaml Normal file
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structures:
main:
bits: 32
ranges:
31-20:
name: op2
depends-on: 5
values:
0:
description: second operand is an immediate value
structure: immediateOp
1:
description: second operand is a register
structure: registerOp
19-15:
name: rs1
14-12:
name: funct3
description: operation
values:
000: add / sub
100: xor
110: or
111: and
001: sl
101: sr
11-7:
name: rd
6:
name: 0
5:
name: I
4:
name: 1
3:
name: 0
2:
name: 0
1:
name: 1
0:
name: 1
immediateOp:
bits: 12
ranges:
11-0:
name: 12-bit immediate value
description: signed number
registerOp:
bits: 12
ranges:
11-5:
name: funct7
description: function modifier
values:
0000000: default (add, srl)
"0100000": sub, sra
4-0:
name: rs2
description: second register operand

34
gallery/riscv/branch_instr.yaml Normal file
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structures:
main:
bits: 32
ranges:
31-25:
name: imm
24-20:
name: rs2
19-15:
name: rs1
14-12:
name: funct3
description: function modifier
values:
000: if equal
001: if not equal
100: if less
101: if greater or equal
11-7:
name: imm
6:
name: 1
5:
name: 1
4:
name: 0
3:
name: 0
2:
name: 0
1:
name: 1
0:
name: 1

78
gallery/riscv/mem_instr.yaml Normal file
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structures:
main:
bits: 32
ranges:
31-20:
name: src
depends-on: 5
values:
0:
description:
structure: srcImmediate
1:
description:
structure: srcRegister
19-15:
name: rs1
14-12:
name: funct3
description: function modifier
values:
000: byte
001: half-word
"010": word
100: upper byte (load only)
101: upper half (load only)
11-7:
name: dst
depends-on: 5
values:
0:
description:
structure: dstRegister
1:
description:
structure: dstImmediate
6:
name: 0
5:
name: I
4:
name: 0
3:
name: 0
2:
name: 0
1:
name: 1
0:
name: 1
srcImmediate:
bits: 12
ranges:
11-0:
name: src
description: source memory address
srcRegister:
bits: 12
ranges:
11-5:
name: dstU
description: destination address upper bits
4-0:
name: rs2
description: source register
dstImmediate:
bits: 5
ranges:
4-0:
name: destL
description: destination address lower bits
dstRegister:
bits: 5
ranges:
4-0:
name: rd
description: destination register

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gallery/riscv/riscv.pdf Normal file
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14
gallery/riscv/riscv.typ Normal file
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#import "../../src/lib.typ": *
#let conf = config.config(
full-page: true,
left-labels: true
)
#let alu = schema.load("/gallery/riscv/alu_instr.yaml")
#schema.render(alu, config: conf)
#let branch = schema.load("/gallery/riscv/branch_instr.yaml")
#schema.render(branch, config: conf)
#let mem = schema.load("/gallery/riscv/mem_instr.yaml")
#schema.render(mem, config: conf)

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gallery/test.pdf
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1
src/renderer.typ
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@ -410,7 +410,6 @@
shapes += draw-text(range_.name, txt-col, name-x, name-y, fill: bg-col) shapes += draw-text(range_.name, txt-col, name-x, name-y, fill: bg-col)
if range_.description != "" { if range_.description != "" {
//draw.circle((desc-x, -desc-y), radius: 5, fill: red)
let shapes_ let shapes_
(shapes_, desc-x, desc-y) = draw-description( (shapes_, desc-x, desc-y) = draw-description(
config, range_, start-x, bits-y, width, desc-x, desc-y config, range_, start-x, bits-y, width, desc-x, desc-y