Klagarge/Cursor
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Rémi Heredero
2021-11-24 10:50:51 +01:00
commit c7ba678fbb
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Libs/Gates/hdl/mux4to1Signed_sim.vhd Normal file
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ARCHITECTURE sim OF mux4to1Signed IS
BEGIN
muxSelect: process(sel, in0, in1, in2, in3)
begin
case to_integer(sel) is
when 0 => muxOut <= in0 after delay;
when 1 => muxOut <= in1 after delay;
when 2 => muxOut <= in2 after delay;
when 3 => muxOut <= in3 after delay;
when others => muxOut <= (others => 'X') after delay;
end case;
end process muxSelect;
END ARCHITECTURE sim;