Klagarge/Cursor
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Rémi Heredero
2021-11-24 10:50:51 +01:00
commit c7ba678fbb
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Libs/Gates/hdl/or5_m_sim.vhd Normal file
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ARCHITECTURE sim OF or5_m IS
BEGIN
out1 <= in1 or in2 or in3 or in4 or in5 after delay;
END ARCHITECTURE sim;