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Rémi Heredero
2021-11-24 10:50:51 +01:00
commit c7ba678fbb
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Libs/Gates/hdl/xor4_sim.vhd Normal file
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ARCHITECTURE sim OF xor4 IS
BEGIN
xorOut <= in1 xor in2 xor in3 xor in4 after delay;
END ARCHITECTURE sim;