Initial commit

Libs/IO/hdl/tristateBufferSigned_sim.vhd

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+ARCHITECTURE sim OF tristateBufferSigned IS
+BEGIN
+  out1 <= in1 after delay when OE = '1' else (others => 'Z') after delay;
+END ARCHITECTURE sim;
+

Libs/IO/hdl/tristateBufferULogicVector_sim.vhd

@@ -0,0 +1,5 @@
+ARCHITECTURE sim OF tristateBufferULogicVector IS
+BEGIN
+  out1 <= std_logic_vector(in1) after delay when OE = '1' else (others => 'Z') after delay;
+END ARCHITECTURE sim;
+

Libs/IO/hdl/tristateBufferULogic_sim.vhd

@@ -0,0 +1,5 @@
+ARCHITECTURE sim OF tristateBufferULogic IS
+BEGIN
+  out1 <= in1 after delay when OE = '1' else 'Z' after delay;
+END ARCHITECTURE sim;
+

Libs/IO/hdl/tristateBufferUnsigned_sim.vhd

@@ -0,0 +1,5 @@
+ARCHITECTURE sim OF tristateBufferUnsigned IS
+BEGIN
+  out1 <= in1 after delay when OE = '1' else (others => 'Z') after delay;
+END ARCHITECTURE sim;
+

Libs/IO/hds/.hdlsidedata/_tristateBufferSigned_sim.vhd._fpf

@@ -0,0 +1,4 @@
+INCLUDE list {
+ DEFAULT atom 1
+}
+DIALECT atom VHDL_2008

Libs/IO/hds/.hdlsidedata/_tristateBufferULogicVector_sim.vhd._fpf

@@ -0,0 +1,4 @@
+INCLUDE list {
+ DEFAULT atom 1
+}
+DIALECT atom VHDL_2008

Libs/IO/hds/.hdlsidedata/_tristateBufferULogic_sim.vhd._fpf

@@ -0,0 +1,4 @@
+INCLUDE list {
+ DEFAULT atom 1
+}
+DIALECT atom VHDL_2008

Libs/IO/hds/.hdlsidedata/_tristateBufferUnsigned_sim.vhd._fpf

@@ -0,0 +1,4 @@
+INCLUDE list {
+ DEFAULT atom 1
+}
+DIALECT atom VHDL_2008

Libs/IO/hds/.hdlsidedata/_tristatebuffersigned_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/IO/hds/.hdlsidedata/_tristatebufferulogic_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/IO/hds/.hdlsidedata/_tristatebufferulogicvector_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/IO/hds/.hdlsidedata/_tristatebufferunsigned_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/IO/hds/_tristatebuffersigned._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom sim
+DEFAULT_FILE atom tristateBufferSigned_sim.vhd

Libs/IO/hds/_tristatebufferulogicvector._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom sim
+DEFAULT_FILE atom tristateBufferULogicVector_sim.vhd