Initial commit

Libs/Sequential/hdl/DFF_pre_sim.vhd

@@ -0,0 +1,13 @@
+ARCHITECTURE sim OF DFF_pre IS
+BEGIN
+
+  process(clk, pre)
+  begin
+    if pre = '1' then
+      q <= '1' after delay;
+    elsif rising_edge(clk) then
+      q <= d after delay;
+    end if;
+  end process;
+
+END sim;