Initial commit

Libs/Sequential/hdl/counterRestart_RTL.vhd

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+ARCHITECTURE RTL OF counterRestart IS
+
+  signal count: unsigned(countOut'range);
+
+BEGIN
+
+  countWithRestart: process(reset, clock)
+  begin
+    if reset = '1' then
+      count <= (others => '0');
+    elsif rising_edge(clock) then
+      if restart = '1' then
+        count <= (others => '0');
+      else
+        count <= count+1;
+      end if;
+    end if;
+  end process countWithRestart;
+
+  countOut <= count after delay;
+
+END ARCHITECTURE RTL;