SEm-ExamMidterm2024/VHD/hds/ex_24_1_2/@r@t@l.vhd

architecture RTL of ex_07_1 is
begin
  process(gainIn)
  begin
    gainOut <= resize(gainIn, gainOut'length) + shift_left(resize(gainIn, gainOut'length), 1);
  end process;
end RTL;