1617 lines
20 KiB
Plaintext
1617 lines
20 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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ordering 1
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suid 2007,0
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optionalChildren [
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port (LogicalPort
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m 1
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o 2
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suid 2,0
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)
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uid 152,0
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)
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*3 (LogPort
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port (LogicalPort
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decl (Decl
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n "motorOn"
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t "std_ulogic"
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suid 1,0
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)
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tm "RefLabelColHdrMgr"
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tm "RowExpandColHdrMgr"
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)
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tm "GroupColHdrMgr"
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*10 (NameColHdr
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tm "NameColHdrMgr"
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)
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tm "ModeColHdrMgr"
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*12 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*13 (BoundsColHdr
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tm "BoundsColHdrMgr"
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*14 (InitColHdr
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tm "InitColHdrMgr"
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)
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*15 (EolColHdr
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tm "EolColHdrMgr"
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)
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*16 (LogPort
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port (LogicalPort
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decl (Decl
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n "right_left"
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t "std_ulogic"
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o 3
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suid 2004,0
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)
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)
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uid 277,0
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)
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*17 (LogPort
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port (LogicalPort
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decl (Decl
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n "pwm"
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t "std_ulogic"
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o 4
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suid 2005,0
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)
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)
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uid 279,0
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)
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*18 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "side2"
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t "std_ulogic"
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o 5
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suid 2007,0
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)
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)
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uid 357,0
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)
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]
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)
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pdm (PhysicalDM
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uid 154,0
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optionalChildren [
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*19 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "courier,10,0"
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emptyMRCItem *20 (MRCItem
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litem &1
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pos 5
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dimension 20
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uid 95,0
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optionalChildren [
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*21 (MRCItem
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litem &4
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pos 0
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dimension 20
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uid 98,0
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)
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*22 (MRCItem
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litem &5
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pos 1
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dimension 23
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uid 100,0
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)
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*23 (MRCItem
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litem &6
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pos 2
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hidden 1
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dimension 20
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uid 102,0
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)
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*24 (MRCItem
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litem &2
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pos 1
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dimension 20
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uid 121,0
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*25 (MRCItem
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litem &3
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pos 0
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dimension 20
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uid 122,0
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*26 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 278,0
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*27 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 280,0
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)
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*28 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 358,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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textAngle 90
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uid 96,0
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optionalChildren [
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*29 (MRCItem
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litem &7
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pos 0
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dimension 20
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uid 104,0
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)
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*30 (MRCItem
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litem &9
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pos 1
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dimension 50
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uid 108,0
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)
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*31 (MRCItem
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litem &10
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pos 2
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dimension 100
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uid 110,0
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)
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*32 (MRCItem
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litem &11
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pos 3
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dimension 50
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uid 112,0
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)
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*33 (MRCItem
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litem &12
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pos 4
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dimension 100
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uid 114,0
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)
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*34 (MRCItem
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litem &13
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pos 5
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dimension 100
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uid 116,0
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)
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*35 (MRCItem
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litem &14
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pos 6
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dimension 50
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uid 118,0
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)
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*36 (MRCItem
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litem &15
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pos 7
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dimension 80
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uid 120,0
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)
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]
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)
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fixedCol 4
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fixedRow 2
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name "Ports"
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uid 94,0
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vaOverrides [
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]
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)
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]
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)
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uid 150,0
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)
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genericsCommonDM (CommonDM
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ldm (LogicalDM
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emptyRow *37 (LEmptyRow
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uid 156,0
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optionalChildren [
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*38 (RefLabelRowHdr
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)
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*39 (TitleRowHdr
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)
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*40 (FilterRowHdr
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)
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*41 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*42 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*43 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*44 (NameColHdr
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tm "GenericNameColHdrMgr"
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)
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*45 (TypeColHdr
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tm "GenericTypeColHdrMgr"
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)
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*46 (InitColHdr
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tm "GenericValueColHdrMgr"
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)
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*47 (PragmaColHdr
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tm "GenericPragmaColHdrMgr"
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)
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*48 (EolColHdr
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tm "GenericEolColHdrMgr"
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)
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]
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)
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pdm (PhysicalDM
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uid 157,0
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optionalChildren [
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*49 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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emptyMRCItem *50 (MRCItem
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litem &37
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pos 0
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dimension 20
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)
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uid 124,0
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optionalChildren [
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*51 (MRCItem
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litem &38
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pos 0
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dimension 20
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uid 127,0
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)
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*52 (MRCItem
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litem &39
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pos 1
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dimension 23
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uid 129,0
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)
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*53 (MRCItem
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litem &40
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pos 2
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hidden 1
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dimension 20
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uid 131,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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font "courier,10,0"
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textAngle 90
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)
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uid 125,0
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optionalChildren [
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*54 (MRCItem
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litem &41
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pos 0
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dimension 20
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uid 133,0
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*55 (MRCItem
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litem &43
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pos 1
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dimension 50
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uid 137,0
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)
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*56 (MRCItem
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litem &44
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pos 2
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dimension 100
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uid 139,0
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*57 (MRCItem
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litem &45
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pos 3
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dimension 100
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uid 141,0
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)
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*58 (MRCItem
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litem &46
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pos 4
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dimension 50
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uid 143,0
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)
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*59 (MRCItem
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litem &47
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pos 5
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dimension 50
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uid 145,0
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)
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*60 (MRCItem
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litem &48
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pos 6
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dimension 80
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uid 147,0
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)
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]
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)
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fixedCol 3
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fixedRow 2
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name "Ports"
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uid 123,0
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vaOverrides [
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]
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)
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]
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)
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uid 155,0
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type 1
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)
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
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value " "
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)
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(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hdl"
|
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)
|
|
(vvPair
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|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hds/ex_19_1_1/symbol.sb.info"
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)
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(vvPair
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|
variable "SideDataUserDir"
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value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hds/ex_19_1_1/symbol.sb.user"
|
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)
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(vvPair
|
|
variable "SourceDir"
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value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hds"
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|
)
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(vvPair
|
|
variable "appl"
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value "HDL Designer"
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)
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(vvPair
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|
variable "arch_name"
|
|
value "symbol"
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|
)
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|
(vvPair
|
|
variable "concat_file"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
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)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hds/ex_19_1_1"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hds/ex_19_1_1"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "03/27/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
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|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "27"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "ex_19_1_1"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "03/27/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "09:18:55"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "VHD"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Generic_1_file"
|
|
value "D:\\Users\\FCo_HEVs\\Cours\\SEm\\Examens HDL\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\FCo_HEVs\\Cours\\SEm\\Examens HDL\\VHDL_comp"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Exam/VHD/work"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_SpyGlass"
|
|
value "D:\\Users\\FCo_HEVs\\Cours\\SEm\\Examens HDL\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "03"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "ex_19_1_1"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Mar"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "March"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hds/ex_19_1_1/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hds/ex_19_1_1/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "/usr/opt/Modelsim/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
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