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Klagarge 712b2cabb6 finish exam

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Prefs

finish exam

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Simulation

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VHD

finish exam

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VHD_test

finish exam

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.gitignore

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.unorderedFilePath

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hdl_designer.bash

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hdlDesigner.bat

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S

Description

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154 KiB

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Languages

VHDL 45.6%

Go Template 13.7%

SystemVerilog 10.3%

Rocq Prover 7.5%

Coq 7.5%

Other 15.4%