1
0
SEm-Labos/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCalculatePolynom_studentVersion.vhd

39 lines
983 B
VHDL
Raw Permalink Normal View History

2024-02-23 13:01:05 +00:00
ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS
2024-03-10 20:50:07 +00:00
2024-03-13 13:21:54 +00:00
subtype st is signed(coeffBitNb-1+oversamplingBitNb+8 DOWNTO 0);
signal x: st;
signal u: st;
signal v: st;
signal w: st;
2024-03-10 20:50:07 +00:00
2024-02-23 13:01:05 +00:00
BEGIN
2024-03-10 20:50:07 +00:00
process(clock, reset) begin
if reset = '1' then
2024-03-13 13:21:54 +00:00
x <= (others => '0');
u <= (others => '0');
v <= (others => '0');
w <= (others => '0');
2024-03-10 20:50:07 +00:00
elsif rising_edge(clock) then
if restartPolynom = '1' then
2024-03-10 20:50:07 +00:00
2024-03-15 13:03:21 +00:00
x <= resize(d, st'high+1) sla (oversamplingBitNb * 3 + 1);
u <= resize(a, st'high+1) + (resize(b, st'high+1) sla oversamplingBitNb) + (resize(c, st'high+1) sla (oversamplingBitNb*2));
v <= resize(6*a, v'length) + (resize(b, st'high+1) sla (oversamplingBitNb + 1));
2024-03-13 13:21:54 +00:00
w <= resize(6*a, w'length);
else
2024-03-10 20:50:07 +00:00
2024-03-13 13:21:54 +00:00
x <= x + u;
u <= u + v;
v <= v + w;
end if;
2024-03-13 13:21:54 +00:00
2024-03-10 20:50:07 +00:00
end if;
end process;
2024-03-15 13:03:21 +00:00
sampleOut <= resize(x sra (oversamplingBitNb * 3 + 1),signalBitNb);
2024-02-23 13:01:05 +00:00
END ARCHITECTURE studentVersion;