start gpio
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@ -17,17 +17,46 @@
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-- Read registers
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-- 00, data register provides the values detected on the lines.
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--
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signal addresses is unsigned(32 downto 0);
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signal bRead is std_ulogic;
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signal bWrite is std_ulogic;
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ARCHITECTURE studentVersion OF ahbGpio IS
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BEGIN
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process(hReset_n, hClk) begin
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if hReset_n = '1' then
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-- AHB-Lite
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hRData <= (OTHERS => '0');
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hReady <= '0';
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hResp <= '0';
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-- Out
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ioOut <= (OTHERS => '0');
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ioEn <= (OTHERS => '0');
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addresses <= (OTHERS => '0');
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bRead <= '0';
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bWrite <= '1';
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elsif rising_edge(hClk) then
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if hSel = '1' then
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CASE hAddr is
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WHEN 00 =>
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WHEN 01 =>
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WHEN OTHERS
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end CASE;
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end if;
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end if;
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end process;
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-- AHB-Lite
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hRData <= (OTHERS => '0');
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hReady <= '0';
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hResp <= '0';
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-- hRData <= (OTHERS => '0');
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-- hReady <= '0';
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-- hResp <= '0';
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-- Out
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ioOut <= (OTHERS => '0');
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ioEn <= (OTHERS => '0');
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-- ioOut <= (OTHERS => '0');
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-- ioEn <= (OTHERS => '0');
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END ARCHITECTURE studentVersion;
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@ -0,0 +1,38 @@
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-- VHDL Entity AhbLiteComponents.ahbGpio.symbol
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--
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-- Created:
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-- by - remi.heredero.UNKNOWN (WE2330808)
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-- at - 15:08:33 23.02.2024
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY AhbLite;
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USE AhbLite.ahbLite.all;
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ENTITY ahbGpio IS
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GENERIC(
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ioNb : positive := 8
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);
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PORT(
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hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
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hClk : IN std_uLogic;
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hReset_n : IN std_uLogic;
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hSel : IN std_uLogic;
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hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
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hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hWrite : IN std_uLogic;
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ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0);
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hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
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hReady : OUT std_uLogic;
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hResp : OUT std_uLogic;
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ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0);
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ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0)
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);
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-- Declarations
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END ahbGpio ;
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