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add polygon signal

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This commit is contained in:
Rémi Heredero
2024-03-01 14:24:40 +01:00
parent b8b5c00ac2
commit 27e755cc2f
13 changed files with 2799 additions and 754 deletions
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26
01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg
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@ -3,7 +3,7 @@
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 11:05:34 27.02.2024
-- at - 13:13:41 01.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
@ -18,16 +18,20 @@ ARCHITECTURE struct OF waveformGen_tb IS
-- Architecture declarations
constant bitNb: positive := 16;
constant signalBitNb: positive := 16;
constant phaseBitNb: positive := 16;
constant clockFrequency: real := 60.0E6;
--constant clockFrequency: real := 66.0E6;
-- Internal signal declarations
SIGNAL clock : std_ulogic;
SIGNAL en : std_ulogic;
SIGNAL polygon : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL reset : std_ulogic;
SIGNAL sawtooth : unsigned(bitNb-1 DOWNTO 0);
SIGNAL square : unsigned(bitNb-1 DOWNTO 0);
SIGNAL sawtooth : unsigned(phaseBitNb-1 DOWNTO 0);
SIGNAL square : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL step : unsigned(bitNb-1 DOWNTO 0);
SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0);
-- Component Declarations
@ -51,11 +55,15 @@ ARCHITECTURE struct OF waveformGen_tb IS
COMPONENT waveformGen_tester
GENERIC (
bitNb : positive := 16;
clockFrequency : real := 60.0E6
clockFrequency : real := 60.0E6;
phaseBitNb : positive := 16;
signalBitNb : positive := 16
);
PORT (
sawtooth : IN unsigned (bitNb-1 DOWNTO 0);
square : IN unsigned (bitNb-1 DOWNTO 0);
polygon : IN unsigned (signalBitNb-1 DOWNTO 0);
sawtooth : IN unsigned (phaseBitNb-1 DOWNTO 0);
square : IN unsigned (signalBitNb-1 DOWNTO 0);
triangle : IN unsigned (signalBitNb-1 DOWNTO 0);
clock : OUT std_ulogic ;
en : OUT std_ulogic ;
reset : OUT std_ulogic ;
@ -83,11 +91,11 @@ BEGIN
en => en,
reset => reset,
step => step,
polygon => OPEN,
polygon => polygon,
sawtooth => sawtooth,
sine => OPEN,
square => square,
triangle => OPEN
triangle => triangle
);
I_tb : waveformGen_tester
GENERIC MAP (
@ -95,8 +103,10 @@ BEGIN
clockFrequency => clockFrequency
)
PORT MAP (
polygon => polygon,
sawtooth => sawtooth,
square => square,
triangle => triangle,
clock => clock,
en => en,
reset => reset,

12
01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tester_entity.vhg
View File

@ -2,7 +2,7 @@
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 11:05:34 27.02.2024
-- at - 13:12:24 01.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
@ -13,11 +13,15 @@ LIBRARY ieee;
ENTITY waveformGen_tester IS
GENERIC(
bitNb : positive := 16;
clockFrequency : real := 60.0E6
clockFrequency : real := 60.0E6;
phaseBitNb : positive := 16;
signalBitNb : positive := 16
);
PORT(
sawtooth : IN unsigned (BitNb-1 DOWNTO 0);
square : IN unsigned (BitNb-1 DOWNTO 0);
polygon : IN unsigned (signalBitNb-1 DOWNTO 0);
sawtooth : IN unsigned (phaseBitNb-1 DOWNTO 0);
square : IN unsigned (signalBitNb-1 DOWNTO 0);
triangle : IN unsigned (signalBitNb-1 DOWNTO 0);
clock : OUT std_ulogic;
en : OUT std_ulogic;
reset : OUT std_ulogic;