add encoding SM --not finish yet
This commit is contained in:
@ -1,8 +1,8 @@
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-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol
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-- VHDL Entity Board.lissajousGenerator_circuit_EBS2.symbol
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 17:45:49 01.05.2023
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-- by - francois.francois (Aphelia)
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-- at - 13:07:18 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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||||
--
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@ -10,7 +10,10 @@ LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY lissajousGenerator_circuit_EBS3 IS
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ENTITY lissajousGenerator_circuit_EBS2 IS
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GENERIC(
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bitNb : positive := 16
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);
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PORT(
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clock : IN std_ulogic;
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reset_N : IN std_ulogic;
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@ -21,7 +24,7 @@ ENTITY lissajousGenerator_circuit_EBS3 IS
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-- Declarations
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END lissajousGenerator_circuit_EBS3 ;
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END lissajousGenerator_circuit_EBS2 ;
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@ -1340,109 +1343,12 @@ END struct;
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-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
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-- Module Version: 5.7
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--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc
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-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks
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library IEEE;
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use IEEE.std_logic_1164.all;
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library ECP5U;
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use ECP5U.components.all;
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ENTITY pll IS
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PORT(
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clkIn100M : IN std_ulogic;
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en75M : IN std_ulogic;
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en50M : IN std_ulogic;
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en10M : IN std_ulogic;
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clk60MHz : OUT std_ulogic;
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clk75MHz : OUT std_ulogic;
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clk50MHz : OUT std_ulogic;
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clk10MHz : OUT std_ulogic;
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pllLocked : OUT std_ulogic
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);
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-- Declarations
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END pll ;
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architecture rtl of pll is
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-- internal signal declarations
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signal REFCLK: std_logic;
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signal CLKOS3_t: std_logic;
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signal CLKOS2_t: std_logic;
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signal CLKOS_t: std_logic;
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signal CLKOP_t: std_logic;
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signal scuba_vhi: std_logic;
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signal scuba_vlo: std_logic;
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attribute FREQUENCY_PIN_CLKOS3 : string;
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attribute FREQUENCY_PIN_CLKOS2 : string;
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attribute FREQUENCY_PIN_CLKOS : string;
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attribute FREQUENCY_PIN_CLKOP : string;
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attribute FREQUENCY_PIN_CLKI : string;
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attribute ICP_CURRENT : string;
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attribute LPF_RESISTOR : string;
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attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000";
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attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
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attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000";
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attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000";
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attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
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attribute ICP_CURRENT of PLLInst_0 : label is "5";
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attribute LPF_RESISTOR of PLLInst_0 : label is "16";
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attribute syn_keep : boolean;
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attribute NGD_DRC_MASK : integer;
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attribute NGD_DRC_MASK of rtl : architecture is 1;
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begin
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-- component instantiation statements
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scuba_vhi_inst: VHI
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port map (Z=>scuba_vhi);
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scuba_vlo_inst: VLO
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port map (Z=>scuba_vlo);
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PLLInst_0: EHXPLLL
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generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
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STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
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CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0,
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CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7,
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CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0,
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CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
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CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
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OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
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OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
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OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
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OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60,
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CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3,
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CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
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port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
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PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
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PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
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STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
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ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M,
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ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
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CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked,
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INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
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clk10MHz <= CLKOS3_t;
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clk50MHz <= CLKOS2_t;
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clk75MHz <= CLKOS_t;
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clk60MHz <= CLKOP_t;
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end rtl;
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--
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-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion
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-- VHDL Architecture Board.lissajousGenerator_circuit_EBS2.masterVersion
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 17:45:49 01.05.2023
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-- at - 14:46:55 28.04.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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@ -1451,10 +1357,9 @@ LIBRARY ieee;
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USE ieee.numeric_std.all;
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LIBRARY Board;
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LIBRARY Lattice;
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LIBRARY Lissajous;
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ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
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ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS2 IS
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-- Architecture declarations
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constant signalBitNb: positive := 16;
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@ -1463,12 +1368,10 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
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constant stepY: positive := 4;
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-- Internal signal declarations
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SIGNAL clkSys : std_ulogic;
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SIGNAL logic0 : std_ulogic;
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SIGNAL logic1 : std_uLogic;
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SIGNAL reset : std_ulogic;
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SIGNAL resetSynch : std_ulogic;
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SIGNAL resetSynch_N : std_ulogic;
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SIGNAL logic1 : std_uLogic;
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SIGNAL reset : std_ulogic;
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SIGNAL resetSnch_N : std_ulogic;
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SIGNAL resetSynch : std_ulogic;
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-- Component Declarations
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@ -1486,19 +1389,6 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
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out1 : OUT std_uLogic
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);
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END COMPONENT;
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COMPONENT pll
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PORT (
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clkIn100M : IN std_ulogic ;
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en75M : IN std_ulogic ;
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en50M : IN std_ulogic ;
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en10M : IN std_ulogic ;
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clk60MHz : OUT std_ulogic ;
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clk75MHz : OUT std_ulogic ;
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clk50MHz : OUT std_ulogic ;
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clk10MHz : OUT std_ulogic ;
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pllLocked : OUT std_ulogic
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);
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END COMPONENT;
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COMPONENT lissajousGenerator
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GENERIC (
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signalBitNb : positive := 16;
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@ -1520,18 +1410,14 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
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FOR ALL : DFF USE ENTITY Board.DFF;
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FOR ALL : inverterIn USE ENTITY Board.inverterIn;
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FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
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FOR ALL : pll USE ENTITY Lattice.pll;
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-- pragma synthesis_on
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BEGIN
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 5 eb5
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-- HDL Embedded Text Block 4 eb4
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logic1 <= '1';
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-- HDL Embedded Text Block 6 eb6
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logic0 <= '0';
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-- Instance port mappings.
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I_dff : DFF
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@ -1539,7 +1425,7 @@ BEGIN
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CLK => clock,
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CLR => reset,
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D => logic1,
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Q => resetSynch_N
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Q => resetSnch_N
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);
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I_inv1 : inverterIn
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PORT MAP (
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@ -1548,21 +1434,9 @@ BEGIN
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);
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I_inv2 : inverterIn
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PORT MAP (
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in1 => resetSynch_N,
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in1 => resetSnch_N,
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out1 => resetSynch
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);
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U_pll : pll
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PORT MAP (
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clkIn100M => clock,
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en75M => logic0,
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en50M => logic0,
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en10M => logic0,
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clk60MHz => clkSys,
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clk75MHz => OPEN,
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clk50MHz => OPEN,
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clk10MHz => OPEN,
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pllLocked => OPEN
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);
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I_main : lissajousGenerator
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GENERIC MAP (
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signalBitNb => signalBitNb,
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@ -1571,7 +1445,7 @@ BEGIN
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stepY => stepY
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)
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PORT MAP (
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clock => clkSys,
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clock => clock,
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reset => resetSynch,
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triggerOut => triggerOut,
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xOut => xOut,
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@ -1,8 +1,8 @@
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-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol
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-- VHDL Entity Board.lissajousGenerator_circuit_EBS2.symbol
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 17:45:49 01.05.2023
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-- by - francois.francois (Aphelia)
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-- at - 13:07:18 02/19/19
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--
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||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
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@ -10,7 +10,10 @@ LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY lissajousGenerator_circuit_EBS3 IS
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ENTITY lissajousGenerator_circuit_EBS2 IS
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GENERIC(
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bitNb : positive := 16
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);
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PORT(
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clock : IN std_ulogic;
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reset_N : IN std_ulogic;
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@ -21,7 +24,7 @@ ENTITY lissajousGenerator_circuit_EBS3 IS
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-- Declarations
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END lissajousGenerator_circuit_EBS3 ;
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END lissajousGenerator_circuit_EBS2 ;
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@ -1340,109 +1343,12 @@ END struct;
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-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
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-- Module Version: 5.7
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--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc
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-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks
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library IEEE;
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use IEEE.std_logic_1164.all;
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library ECP5U;
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use ECP5U.components.all;
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ENTITY pll IS
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PORT(
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clkIn100M : IN std_ulogic;
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en75M : IN std_ulogic;
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en50M : IN std_ulogic;
|
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en10M : IN std_ulogic;
|
||||
clk60MHz : OUT std_ulogic;
|
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clk75MHz : OUT std_ulogic;
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clk50MHz : OUT std_ulogic;
|
||||
clk10MHz : OUT std_ulogic;
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pllLocked : OUT std_ulogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END pll ;
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||||
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architecture rtl of pll is
|
||||
|
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-- internal signal declarations
|
||||
signal REFCLK: std_logic;
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signal CLKOS3_t: std_logic;
|
||||
signal CLKOS2_t: std_logic;
|
||||
signal CLKOS_t: std_logic;
|
||||
signal CLKOP_t: std_logic;
|
||||
signal scuba_vhi: std_logic;
|
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signal scuba_vlo: std_logic;
|
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|
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attribute FREQUENCY_PIN_CLKOS3 : string;
|
||||
attribute FREQUENCY_PIN_CLKOS2 : string;
|
||||
attribute FREQUENCY_PIN_CLKOS : string;
|
||||
attribute FREQUENCY_PIN_CLKOP : string;
|
||||
attribute FREQUENCY_PIN_CLKI : string;
|
||||
attribute ICP_CURRENT : string;
|
||||
attribute LPF_RESISTOR : string;
|
||||
attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000";
|
||||
attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
|
||||
attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000";
|
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attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000";
|
||||
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
|
||||
attribute ICP_CURRENT of PLLInst_0 : label is "5";
|
||||
attribute LPF_RESISTOR of PLLInst_0 : label is "16";
|
||||
attribute syn_keep : boolean;
|
||||
attribute NGD_DRC_MASK : integer;
|
||||
attribute NGD_DRC_MASK of rtl : architecture is 1;
|
||||
|
||||
begin
|
||||
-- component instantiation statements
|
||||
scuba_vhi_inst: VHI
|
||||
port map (Z=>scuba_vhi);
|
||||
|
||||
scuba_vlo_inst: VLO
|
||||
port map (Z=>scuba_vlo);
|
||||
|
||||
PLLInst_0: EHXPLLL
|
||||
generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
|
||||
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
|
||||
CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0,
|
||||
CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7,
|
||||
CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0,
|
||||
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
|
||||
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
|
||||
OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
|
||||
OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
|
||||
OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
|
||||
OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60,
|
||||
CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3,
|
||||
CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
|
||||
port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
|
||||
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
|
||||
PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
|
||||
STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
|
||||
ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M,
|
||||
ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
|
||||
CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked,
|
||||
INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
|
||||
|
||||
clk10MHz <= CLKOS3_t;
|
||||
clk50MHz <= CLKOS2_t;
|
||||
clk75MHz <= CLKOS_t;
|
||||
clk60MHz <= CLKOP_t;
|
||||
end rtl;
|
||||
|
||||
|
||||
|
||||
|
||||
--
|
||||
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion
|
||||
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS2.masterVersion
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 17:45:49 01.05.2023
|
||||
-- at - 14:46:55 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
@ -1451,10 +1357,9 @@ LIBRARY ieee;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
-- LIBRARY Board;
|
||||
-- LIBRARY Lattice;
|
||||
-- LIBRARY Lissajous;
|
||||
|
||||
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
||||
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS2 IS
|
||||
|
||||
-- Architecture declarations
|
||||
constant signalBitNb: positive := 16;
|
||||
@ -1463,12 +1368,10 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
||||
constant stepY: positive := 4;
|
||||
|
||||
-- Internal signal declarations
|
||||
SIGNAL clkSys : std_ulogic;
|
||||
SIGNAL logic0 : std_ulogic;
|
||||
SIGNAL logic1 : std_uLogic;
|
||||
SIGNAL reset : std_ulogic;
|
||||
SIGNAL resetSynch : std_ulogic;
|
||||
SIGNAL resetSynch_N : std_ulogic;
|
||||
SIGNAL logic1 : std_uLogic;
|
||||
SIGNAL reset : std_ulogic;
|
||||
SIGNAL resetSnch_N : std_ulogic;
|
||||
SIGNAL resetSynch : std_ulogic;
|
||||
|
||||
|
||||
-- Component Declarations
|
||||
@ -1486,19 +1389,6 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
||||
out1 : OUT std_uLogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT pll
|
||||
PORT (
|
||||
clkIn100M : IN std_ulogic ;
|
||||
en75M : IN std_ulogic ;
|
||||
en50M : IN std_ulogic ;
|
||||
en10M : IN std_ulogic ;
|
||||
clk60MHz : OUT std_ulogic ;
|
||||
clk75MHz : OUT std_ulogic ;
|
||||
clk50MHz : OUT std_ulogic ;
|
||||
clk10MHz : OUT std_ulogic ;
|
||||
pllLocked : OUT std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT lissajousGenerator
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16;
|
||||
@ -1520,18 +1410,14 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
||||
-- FOR ALL : DFF USE ENTITY Board.DFF;
|
||||
-- FOR ALL : inverterIn USE ENTITY Board.inverterIn;
|
||||
-- FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
|
||||
-- FOR ALL : pll USE ENTITY Lattice.pll;
|
||||
-- pragma synthesis_on
|
||||
|
||||
|
||||
BEGIN
|
||||
-- Architecture concurrent statements
|
||||
-- HDL Embedded Text Block 5 eb5
|
||||
-- HDL Embedded Text Block 4 eb4
|
||||
logic1 <= '1';
|
||||
|
||||
-- HDL Embedded Text Block 6 eb6
|
||||
logic0 <= '0';
|
||||
|
||||
|
||||
-- Instance port mappings.
|
||||
I_dff : DFF
|
||||
@ -1539,7 +1425,7 @@ BEGIN
|
||||
CLK => clock,
|
||||
CLR => reset,
|
||||
D => logic1,
|
||||
Q => resetSynch_N
|
||||
Q => resetSnch_N
|
||||
);
|
||||
I_inv1 : inverterIn
|
||||
PORT MAP (
|
||||
@ -1548,21 +1434,9 @@ BEGIN
|
||||
);
|
||||
I_inv2 : inverterIn
|
||||
PORT MAP (
|
||||
in1 => resetSynch_N,
|
||||
in1 => resetSnch_N,
|
||||
out1 => resetSynch
|
||||
);
|
||||
U_pll : pll
|
||||
PORT MAP (
|
||||
clkIn100M => clock,
|
||||
en75M => logic0,
|
||||
en50M => logic0,
|
||||
en10M => logic0,
|
||||
clk60MHz => clkSys,
|
||||
clk75MHz => OPEN,
|
||||
clk50MHz => OPEN,
|
||||
clk10MHz => OPEN,
|
||||
pllLocked => OPEN
|
||||
);
|
||||
I_main : lissajousGenerator
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
@ -1571,7 +1445,7 @@ BEGIN
|
||||
stepY => stepY
|
||||
)
|
||||
PORT MAP (
|
||||
clock => clkSys,
|
||||
clock => clock,
|
||||
reset => resetSynch,
|
||||
triggerOut => triggerOut,
|
||||
xOut => xOut,
|
||||
|
||||
23
zz-solutions/04-Lissajous/Board/hdl/dff_entity.vhg
Normal file
23
zz-solutions/04-Lissajous/Board/hdl/dff_entity.vhg
Normal file
@ -0,0 +1,23 @@
|
||||
-- VHDL Entity Board.DFF.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:07:05 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
ENTITY DFF IS
|
||||
PORT(
|
||||
CLK : IN std_uLogic;
|
||||
CLR : IN std_uLogic;
|
||||
D : IN std_uLogic;
|
||||
Q : OUT std_uLogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END DFF ;
|
||||
|
||||
21
zz-solutions/04-Lissajous/Board/hdl/inverterin_entity.vhg
Normal file
21
zz-solutions/04-Lissajous/Board/hdl/inverterin_entity.vhg
Normal file
@ -0,0 +1,21 @@
|
||||
-- VHDL Entity Board.inverterIn.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:07:14 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
ENTITY inverterIn IS
|
||||
PORT(
|
||||
in1 : IN std_uLogic;
|
||||
out1 : OUT std_uLogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END inverterIn ;
|
||||
|
||||
@ -0,0 +1,28 @@
|
||||
-- VHDL Entity Board.lissajousGenerator_circuit_EBS2.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:07:18 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY lissajousGenerator_circuit_EBS2 IS
|
||||
GENERIC(
|
||||
bitNb : positive := 16
|
||||
);
|
||||
PORT(
|
||||
clock : IN std_ulogic;
|
||||
reset_N : IN std_ulogic;
|
||||
triggerOut : OUT std_ulogic;
|
||||
xOut : OUT std_ulogic;
|
||||
yOut : OUT std_ulogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END lissajousGenerator_circuit_EBS2 ;
|
||||
|
||||
@ -0,0 +1,110 @@
|
||||
--
|
||||
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS2.masterVersion
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 14:46:55 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
LIBRARY Board;
|
||||
LIBRARY Lissajous;
|
||||
|
||||
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS2 IS
|
||||
|
||||
-- Architecture declarations
|
||||
constant signalBitNb: positive := 16;
|
||||
constant phaseBitNb: positive := 17;
|
||||
constant stepX: positive := 3;
|
||||
constant stepY: positive := 4;
|
||||
|
||||
-- Internal signal declarations
|
||||
SIGNAL logic1 : std_uLogic;
|
||||
SIGNAL reset : std_ulogic;
|
||||
SIGNAL resetSnch_N : std_ulogic;
|
||||
SIGNAL resetSynch : std_ulogic;
|
||||
|
||||
|
||||
-- Component Declarations
|
||||
COMPONENT DFF
|
||||
PORT (
|
||||
CLK : IN std_uLogic ;
|
||||
CLR : IN std_uLogic ;
|
||||
D : IN std_uLogic ;
|
||||
Q : OUT std_uLogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT inverterIn
|
||||
PORT (
|
||||
in1 : IN std_uLogic ;
|
||||
out1 : OUT std_uLogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT lissajousGenerator
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16;
|
||||
phaseBitNb : positive := 16;
|
||||
stepX : positive := 1;
|
||||
stepY : positive := 1
|
||||
);
|
||||
PORT (
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
triggerOut : OUT std_ulogic ;
|
||||
xOut : OUT std_ulogic ;
|
||||
yOut : OUT std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Optional embedded configurations
|
||||
-- pragma synthesis_off
|
||||
FOR ALL : DFF USE ENTITY Board.DFF;
|
||||
FOR ALL : inverterIn USE ENTITY Board.inverterIn;
|
||||
FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
|
||||
-- pragma synthesis_on
|
||||
|
||||
|
||||
BEGIN
|
||||
-- Architecture concurrent statements
|
||||
-- HDL Embedded Text Block 4 eb4
|
||||
logic1 <= '1';
|
||||
|
||||
|
||||
-- Instance port mappings.
|
||||
I_dff : DFF
|
||||
PORT MAP (
|
||||
CLK => clock,
|
||||
CLR => reset,
|
||||
D => logic1,
|
||||
Q => resetSnch_N
|
||||
);
|
||||
I_inv1 : inverterIn
|
||||
PORT MAP (
|
||||
in1 => reset_N,
|
||||
out1 => reset
|
||||
);
|
||||
I_inv2 : inverterIn
|
||||
PORT MAP (
|
||||
in1 => resetSnch_N,
|
||||
out1 => resetSynch
|
||||
);
|
||||
I_main : lissajousGenerator
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
phaseBitNb => phaseBitNb,
|
||||
stepX => stepX,
|
||||
stepY => stepY
|
||||
)
|
||||
PORT MAP (
|
||||
clock => clock,
|
||||
reset => resetSynch,
|
||||
triggerOut => triggerOut,
|
||||
xOut => xOut,
|
||||
yOut => yOut
|
||||
);
|
||||
|
||||
END masterVersion;
|
||||
@ -0,0 +1,25 @@
|
||||
-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 17:45:49 01.05.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY lissajousGenerator_circuit_EBS3 IS
|
||||
PORT(
|
||||
clock : IN std_ulogic;
|
||||
reset_N : IN std_ulogic;
|
||||
triggerOut : OUT std_ulogic;
|
||||
xOut : OUT std_ulogic;
|
||||
yOut : OUT std_ulogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END lissajousGenerator_circuit_EBS3 ;
|
||||
|
||||
@ -0,0 +1,142 @@
|
||||
--
|
||||
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 17:45:49 01.05.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
LIBRARY Board;
|
||||
LIBRARY Lattice;
|
||||
LIBRARY Lissajous;
|
||||
|
||||
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
||||
|
||||
-- Architecture declarations
|
||||
constant signalBitNb: positive := 16;
|
||||
constant phaseBitNb: positive := 17;
|
||||
constant stepX: positive := 3;
|
||||
constant stepY: positive := 4;
|
||||
|
||||
-- Internal signal declarations
|
||||
SIGNAL clkSys : std_ulogic;
|
||||
SIGNAL logic0 : std_ulogic;
|
||||
SIGNAL logic1 : std_uLogic;
|
||||
SIGNAL reset : std_ulogic;
|
||||
SIGNAL resetSynch : std_ulogic;
|
||||
SIGNAL resetSynch_N : std_ulogic;
|
||||
|
||||
|
||||
-- Component Declarations
|
||||
COMPONENT DFF
|
||||
PORT (
|
||||
CLK : IN std_uLogic ;
|
||||
CLR : IN std_uLogic ;
|
||||
D : IN std_uLogic ;
|
||||
Q : OUT std_uLogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT inverterIn
|
||||
PORT (
|
||||
in1 : IN std_uLogic ;
|
||||
out1 : OUT std_uLogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT pll
|
||||
PORT (
|
||||
clkIn100M : IN std_ulogic;
|
||||
en10M : IN std_ulogic;
|
||||
en50M : IN std_ulogic;
|
||||
en75M : IN std_ulogic;
|
||||
clk10MHz : OUT std_ulogic;
|
||||
clk50MHz : OUT std_ulogic;
|
||||
clk60MHz : OUT std_ulogic;
|
||||
clk75MHz : OUT std_ulogic;
|
||||
pllLocked : OUT std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT lissajousGenerator
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16;
|
||||
phaseBitNb : positive := 16;
|
||||
stepX : positive := 1;
|
||||
stepY : positive := 1
|
||||
);
|
||||
PORT (
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
triggerOut : OUT std_ulogic ;
|
||||
xOut : OUT std_ulogic ;
|
||||
yOut : OUT std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Optional embedded configurations
|
||||
-- pragma synthesis_off
|
||||
FOR ALL : DFF USE ENTITY Board.DFF;
|
||||
FOR ALL : inverterIn USE ENTITY Board.inverterIn;
|
||||
FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
|
||||
FOR ALL : pll USE ENTITY Lattice.pll;
|
||||
-- pragma synthesis_on
|
||||
|
||||
|
||||
BEGIN
|
||||
-- Architecture concurrent statements
|
||||
-- HDL Embedded Text Block 5 eb5
|
||||
logic1 <= '1';
|
||||
|
||||
-- HDL Embedded Text Block 6 eb6
|
||||
logic0 <= '0';
|
||||
|
||||
|
||||
-- Instance port mappings.
|
||||
I_dff : DFF
|
||||
PORT MAP (
|
||||
CLK => clock,
|
||||
CLR => reset,
|
||||
D => logic1,
|
||||
Q => resetSynch_N
|
||||
);
|
||||
I_inv1 : inverterIn
|
||||
PORT MAP (
|
||||
in1 => reset_N,
|
||||
out1 => reset
|
||||
);
|
||||
I_inv2 : inverterIn
|
||||
PORT MAP (
|
||||
in1 => resetSynch_N,
|
||||
out1 => resetSynch
|
||||
);
|
||||
U_pll : pll
|
||||
PORT MAP (
|
||||
clkIn100M => clock,
|
||||
en75M => logic0,
|
||||
en50M => logic0,
|
||||
en10M => logic0,
|
||||
clk60MHz => clkSys,
|
||||
clk75MHz => OPEN,
|
||||
clk50MHz => OPEN,
|
||||
clk10MHz => OPEN,
|
||||
pllLocked => OPEN
|
||||
);
|
||||
I_main : lissajousGenerator
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
phaseBitNb => phaseBitNb,
|
||||
stepX => stepX,
|
||||
stepY => stepY
|
||||
)
|
||||
PORT MAP (
|
||||
clock => clkSys,
|
||||
reset => resetSynch,
|
||||
triggerOut => triggerOut,
|
||||
xOut => xOut,
|
||||
yOut => yOut
|
||||
);
|
||||
|
||||
END masterVersion;
|
||||
BIN
zz-solutions/04-Lissajous/Board/hds/.cache.dat
Normal file
BIN
zz-solutions/04-Lissajous/Board/hds/.cache.dat
Normal file
Binary file not shown.
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
24
zz-solutions/04-Lissajous/Board/hds/.xrf/dff_entity.xrf
Normal file
24
zz-solutions/04-Lissajous/Board/hds/.xrf/dff_entity.xrf
Normal file
@ -0,0 +1,24 @@
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 98,0 8 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 13 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 63,0 14 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 51,0 15 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 69,0 16 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 19 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 20 0
|
||||
@ -0,0 +1,18 @@
|
||||
DESIGN inverter@in
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN inverter@in
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 41,0 8 0
|
||||
DESIGN inverter@in
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 16,0 13 0
|
||||
DESIGN inverter@in
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 22,0 14 0
|
||||
DESIGN inverter@in
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 31,0 17 0
|
||||
DESIGN inverter@in
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 31,0 18 0
|
||||
@ -0,0 +1,30 @@
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 17 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 18 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 88,0 19 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 93,0 20 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 98,0 21 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 24 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 25 0
|
||||
@ -0,0 +1,165 @@
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 84,0 9 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 12
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 0,0 16 2
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 1,0 19 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 19
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 895,0 25 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 49,0 26 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 893,0 27 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 897,0 28 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 29
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 30
|
||||
LIBRARY Board
|
||||
DESIGN @d@f@f
|
||||
VIEW sim
|
||||
GRAPHIC 1071,0 32 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 34 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 63,0 35 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 51,0 36 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 69,0 37 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 1817,0 40 0
|
||||
DESIGN inverter@in
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 16,0 42 0
|
||||
DESIGN inverter@in
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 22,0 43 0
|
||||
LIBRARY Lissajous
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct
|
||||
GRAPHIC 2310,0 46 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 47 1
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 54 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 428,0 55 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 88,0 56 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 93,0 57 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 98,0 58 0
|
||||
LIBRARY Board
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 61
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 1071,0 64 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 1817,0 65 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 2310,0 66 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 69
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 818,0 72 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 74
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 75
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 1071,0 77 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 873,0 79 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 879,0 80 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 887,0 81 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 883,0 82 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 1817,0 84 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 43,0 86 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 879,0 87 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 1806,0 89 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 883,0 91 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 245,0 92 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 2310,0 94 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 2317,0 95 1
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 15,0 102 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 245,0 103 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 435,0 104 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 575,0 105 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 29,0 106 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 109
|
||||
@ -0,0 +1,27 @@
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 118,0 14 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 128,0 15 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 123,0 16 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 133,0 17 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 138,0 18 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 21 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 22 0
|
||||
@ -0,0 +1,205 @@
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 41,0 9 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 12
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 0,0 17 2
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 1,0 20 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 20
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 380,0 26 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 411,0 27 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 370,0 28 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 360,0 29 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 368,0 30 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 464,0 31 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 32
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 33
|
||||
LIBRARY Board
|
||||
DESIGN @d@f@f
|
||||
VIEW sim
|
||||
GRAPHIC 219,0 35 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 37 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 63,0 38 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 51,0 39 0
|
||||
DESIGN @d@f@f
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 69,0 40 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 199,0 43 0
|
||||
DESIGN inverter@in
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 16,0 45 0
|
||||
DESIGN inverter@in
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 22,0 46 0
|
||||
LIBRARY Board
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version
|
||||
GRAPHIC 168,0 49 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 60
|
||||
LIBRARY Lissajous
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct
|
||||
GRAPHIC 265,0 62 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 63 1
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 70 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 428,0 71 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 88,0 72 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 93,0 73 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 98,0 74 0
|
||||
LIBRARY Board
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 77
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 219,0 80 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 199,0 81 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 265,0 82 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 168,0 83 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 86
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 190,0 89 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 91
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 382,0 92 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 94
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 95
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 219,0 97 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 328,0 99 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 320,0 100 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 338,0 101 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 334,0 102 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 199,0 104 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 348,0 106 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 320,0 107 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 245,0 109 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 334,0 111 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 352,0 112 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 168,0 114 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 312,0 116 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 393,0 117 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 405,0 118 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 399,0 119 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 376,0 120 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 265,0 126 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 272,0 127 1
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 376,0 134 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 352,0 135 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 324,0 136 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 344,0 137 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
GRAPHIC 316,0 138 0
|
||||
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||
VIEW master@version.bd
|
||||
NO_GRAPHIC 141
|
||||
@ -0,0 +1,31 @@
|
||||
-- VHDL Entity Lissajous.lissajousGenerator.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:07:53 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY lissajousGenerator IS
|
||||
GENERIC(
|
||||
signalBitNb : positive := 16;
|
||||
phaseBitNb : positive := 16;
|
||||
stepX : positive := 1;
|
||||
stepY : positive := 1
|
||||
);
|
||||
PORT(
|
||||
clock : IN std_ulogic;
|
||||
reset : IN std_ulogic;
|
||||
triggerOut : OUT std_ulogic;
|
||||
xOut : OUT std_ulogic;
|
||||
yOut : OUT std_ulogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END lissajousGenerator ;
|
||||
|
||||
@ -0,0 +1,126 @@
|
||||
--
|
||||
-- VHDL Architecture Lissajous.lissajousGenerator.struct
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 14:47:09 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
LIBRARY DigitalToAnalogConverter;
|
||||
LIBRARY SplineInterpolator;
|
||||
|
||||
ARCHITECTURE struct OF lissajousGenerator IS
|
||||
|
||||
-- Architecture declarations
|
||||
|
||||
-- Internal signal declarations
|
||||
SIGNAL sineX : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL sineY : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL squareY : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL stepXUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
|
||||
SIGNAL stepYUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
|
||||
|
||||
|
||||
-- Component Declarations
|
||||
COMPONENT DAC
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
serialOut : OUT std_ulogic ;
|
||||
parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT sineGen
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16;
|
||||
phaseBitNb : positive := 10
|
||||
);
|
||||
PORT (
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
|
||||
sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Optional embedded configurations
|
||||
-- pragma synthesis_off
|
||||
FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC;
|
||||
FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen;
|
||||
-- pragma synthesis_on
|
||||
|
||||
|
||||
BEGIN
|
||||
-- Architecture concurrent statements
|
||||
-- HDL Embedded Text Block 1 eb1
|
||||
triggerOut <= squareY(squareY'high);
|
||||
|
||||
-- HDL Embedded Text Block 2 eb2
|
||||
stepXUnsigned <= to_unsigned(stepX, stepXUnsigned'length);
|
||||
|
||||
-- HDL Embedded Text Block 3 eb3
|
||||
stepYUnsigned <= to_unsigned(stepY, stepYUnsigned'length);
|
||||
|
||||
|
||||
-- Instance port mappings.
|
||||
I_dacX : DAC
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
serialOut => xOut,
|
||||
parallelIn => sineX,
|
||||
clock => clock,
|
||||
reset => reset
|
||||
);
|
||||
I_dacY : DAC
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
serialOut => yOut,
|
||||
parallelIn => sineY,
|
||||
clock => clock,
|
||||
reset => reset
|
||||
);
|
||||
I_sinX : sineGen
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
phaseBitNb => phaseBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
step => stepXUnsigned,
|
||||
sawtooth => OPEN,
|
||||
sine => sineX,
|
||||
square => OPEN,
|
||||
triangle => OPEN
|
||||
);
|
||||
I_sinY : sineGen
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
phaseBitNb => phaseBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
step => stepYUnsigned,
|
||||
sawtooth => OPEN,
|
||||
sine => sineY,
|
||||
square => squareY,
|
||||
triangle => OPEN
|
||||
);
|
||||
|
||||
END struct;
|
||||
BIN
zz-solutions/04-Lissajous/Lissajous/hds/.cache.dat
Normal file
BIN
zz-solutions/04-Lissajous/Lissajous/hds/.cache.dat
Normal file
Binary file not shown.
@ -0,0 +1,30 @@
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 20 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 428,0 21 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 88,0 22 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 93,0 23 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 98,0 24 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 27 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 28 0
|
||||
@ -0,0 +1,192 @@
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 84,0 9 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 12
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 0,0 16 2
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 617,0 21 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1631,0 22 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1652,0 23 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2512,0 24 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2510,0 25 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 26
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 27
|
||||
LIBRARY DigitalToAnalogConverter
|
||||
DESIGN @d@a@c
|
||||
VIEW master@version
|
||||
GRAPHIC 2187,0 29 0
|
||||
DESIGN @d@a@c
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 30 1
|
||||
DESIGN @d@a@c
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 67,0 34 0
|
||||
DESIGN @d@a@c
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 35 0
|
||||
DESIGN @d@a@c
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 36 0
|
||||
DESIGN @d@a@c
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 76,0 37 0
|
||||
LIBRARY SplineInterpolator
|
||||
DESIGN sine@gen
|
||||
VIEW struct
|
||||
GRAPHIC 2090,0 40 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 41 1
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 46 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 88,0 47 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 128,0 48 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 98,0 49 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 103,0 50 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 108,0 51 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 118,0 52 0
|
||||
LIBRARY Lissajous
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 55
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2187,0 58 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2090,0 59 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 62
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 443,0 65 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 67
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1324,0 68 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 70
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1637,0 71 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 73
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 74
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2187,0 76 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2194,0 77 1
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 575,0 81 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 579,0 82 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 583,0 83 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 589,0 84 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2162,0 86 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2169,0 87 1
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 29,0 91 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1613,0 92 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1617,0 93 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1623,0 94 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2090,0 96 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2097,0 97 1
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2349,0 102 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2341,0 103 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1335,0 104 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 579,0 106 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2053,0 110 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2060,0 111 1
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 15,0 116 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2357,0 117 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1341,0 118 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1613,0 120 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 450,0 121 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 125
|
||||
@ -0,0 +1,15 @@
|
||||
-- VHDL Entity Lissajous_test.lissajousGenerator_test.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:07:27 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
|
||||
|
||||
ENTITY lissajousGenerator_test IS
|
||||
-- Declarations
|
||||
|
||||
END lissajousGenerator_test ;
|
||||
|
||||
@ -0,0 +1,152 @@
|
||||
--
|
||||
-- VHDL Architecture Lissajous_test.lissajousGenerator_test.struct
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 14:48:46 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY Lissajous;
|
||||
LIBRARY Lissajous_test;
|
||||
LIBRARY WaveformGenerator;
|
||||
|
||||
ARCHITECTURE struct OF lissajousGenerator_test IS
|
||||
|
||||
-- Architecture declarations
|
||||
constant signalBitNb: positive := 16;
|
||||
constant phaseBitNb: positive := 17;
|
||||
constant stepX: positive := 2;
|
||||
constant stepY: positive := 3;
|
||||
constant lowpassShiftBitNb: positive := 8;
|
||||
constant clockFrequency: real := 60.0E6;
|
||||
--constant clockFrequency: real := 66.0E6;
|
||||
|
||||
-- Internal signal declarations
|
||||
SIGNAL clock : std_ulogic;
|
||||
SIGNAL reset : std_ulogic;
|
||||
SIGNAL triggerOut : std_ulogic;
|
||||
SIGNAL xLowapss : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL xParallel : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL xSerial : std_ulogic;
|
||||
SIGNAL yLowpass : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL yParallel : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL ySerial : std_ulogic;
|
||||
|
||||
|
||||
-- Component Declarations
|
||||
COMPONENT lissajousGenerator
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16;
|
||||
phaseBitNb : positive := 16;
|
||||
stepX : positive := 1;
|
||||
stepY : positive := 1
|
||||
);
|
||||
PORT (
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
triggerOut : OUT std_ulogic ;
|
||||
xOut : OUT std_ulogic ;
|
||||
yOut : OUT std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT lissajousGenerator_tester
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16;
|
||||
clockFrequency : real := 60.0E6
|
||||
);
|
||||
PORT (
|
||||
triggerOut : IN std_ulogic ;
|
||||
xLowapss : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
xSerial : IN std_ulogic ;
|
||||
yLowpass : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
ySerial : IN std_ulogic ;
|
||||
clock : OUT std_ulogic ;
|
||||
reset : OUT std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT lowpass
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16;
|
||||
shiftBitNb : positive := 12
|
||||
);
|
||||
PORT (
|
||||
lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Optional embedded configurations
|
||||
-- pragma synthesis_off
|
||||
FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
|
||||
FOR ALL : lissajousGenerator_tester USE ENTITY Lissajous_test.lissajousGenerator_tester;
|
||||
FOR ALL : lowpass USE ENTITY WaveformGenerator.lowpass;
|
||||
-- pragma synthesis_on
|
||||
|
||||
|
||||
BEGIN
|
||||
-- Architecture concurrent statements
|
||||
-- HDL Embedded Text Block 1 eb1
|
||||
xParallel <= (others => xSerial);
|
||||
yParallel <= (others => ySerial);
|
||||
|
||||
|
||||
-- Instance port mappings.
|
||||
I_DUT : lissajousGenerator
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
phaseBitNb => phaseBitNb,
|
||||
stepX => stepX,
|
||||
stepY => stepY
|
||||
)
|
||||
PORT MAP (
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
triggerOut => triggerOut,
|
||||
xOut => xSerial,
|
||||
yOut => ySerial
|
||||
);
|
||||
I_tester : lissajousGenerator_tester
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
clockFrequency => clockFrequency
|
||||
)
|
||||
PORT MAP (
|
||||
triggerOut => triggerOut,
|
||||
xLowapss => xLowapss,
|
||||
xSerial => xSerial,
|
||||
yLowpass => yLowpass,
|
||||
ySerial => ySerial,
|
||||
clock => clock,
|
||||
reset => reset
|
||||
);
|
||||
I_filtX : lowpass
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
shiftBitNb => lowpassShiftBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
lowpassOut => xLowapss,
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
lowpassIn => xParallel
|
||||
);
|
||||
I_filty : lowpass
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
shiftBitNb => lowpassShiftBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
lowpassOut => yLowpass,
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
lowpassIn => yParallel
|
||||
);
|
||||
|
||||
END struct;
|
||||
@ -0,0 +1,31 @@
|
||||
-- VHDL Entity Lissajous_test.lissajousGenerator_tester.interface
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 14:48:11 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY lissajousGenerator_tester IS
|
||||
GENERIC(
|
||||
signalBitNb : positive := 16;
|
||||
clockFrequency : real := 60.0E6
|
||||
);
|
||||
PORT(
|
||||
triggerOut : IN std_ulogic;
|
||||
xLowapss : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
xSerial : IN std_ulogic;
|
||||
yLowpass : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
ySerial : IN std_ulogic;
|
||||
clock : OUT std_ulogic;
|
||||
reset : OUT std_ulogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END lissajousGenerator_tester ;
|
||||
|
||||
BIN
zz-solutions/04-Lissajous/Lissajous_test/hds/.cache.dat
Normal file
BIN
zz-solutions/04-Lissajous/Lissajous_test/hds/.cache.dat
Normal file
Binary file not shown.
@ -0,0 +1,12 @@
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 11 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 12 0
|
||||
@ -0,0 +1,211 @@
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 142,0 9 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 12
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 0,0 17 2
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1,0 20 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 20
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1562,0 29 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1554,0 30 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1827,0 31 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1695,0 32 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1697,0 33 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1693,0 34 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1744,0 35 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1762,0 36 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1683,0 37 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 38
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 39
|
||||
LIBRARY Lissajous
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct
|
||||
GRAPHIC 1594,0 41 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 42 1
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 49 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 428,0 50 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 88,0 51 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 93,0 52 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 98,0 53 0
|
||||
LIBRARY Lissajous_test
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW test
|
||||
GRAPHIC 421,0 56 0
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW interface
|
||||
GRAPHIC 14,0 57 1
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1829,0 62 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1665,0 63 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1687,0 64 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1738,0 65 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1637,0 66 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1564,0 67 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1556,0 68 0
|
||||
LIBRARY WaveformGenerator
|
||||
DESIGN lowpass
|
||||
VIEW master@version
|
||||
GRAPHIC 1612,0 71 0
|
||||
DESIGN lowpass
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 72 1
|
||||
DESIGN lowpass
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 77 0
|
||||
DESIGN lowpass
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 78 0
|
||||
DESIGN lowpass
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 76,0 79 0
|
||||
DESIGN lowpass
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 80 0
|
||||
LIBRARY Lissajous_test
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 83
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1594,0 86 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 421,0 87 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1612,0 88 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 91
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1603,0 94 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 97
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 98
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1594,0 100 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1601,0 101 1
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1564,0 108 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1556,0 109 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1829,0 110 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1687,0 111 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1637,0 112 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 421,0 114 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 428,0 115 1
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1612,0 128 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1619,0 129 1
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1665,0 134 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1659,0 135 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1653,0 136 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1671,0 137 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1699,0 139 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1706,0 140 1
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1738,0 145 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1724,0 146 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1730,0 147 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1756,0 148 0
|
||||
DESIGN lissajous@generator_test
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 151
|
||||
@ -0,0 +1,36 @@
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW interface
|
||||
NO_GRAPHIC 0
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW interface
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW interface
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW interface
|
||||
GRAPHIC 659,0 18 0
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW interface
|
||||
GRAPHIC 664,0 19 0
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW interface
|
||||
GRAPHIC 669,0 20 0
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW interface
|
||||
GRAPHIC 674,0 21 0
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW interface
|
||||
GRAPHIC 679,0 22 0
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW interface
|
||||
GRAPHIC 649,0 23 0
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW interface
|
||||
GRAPHIC 654,0 24 0
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1,0 27 0
|
||||
DESIGN lissajous@generator_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1,0 28 0
|
||||
@ -0,0 +1,55 @@
|
||||
version "8.0"
|
||||
RenoirTeamPreferences [
|
||||
(BaseTeamPreferences
|
||||
version "1.1"
|
||||
verConcat 0
|
||||
ttDGProps [
|
||||
]
|
||||
fcDGProps [
|
||||
]
|
||||
smDGProps [
|
||||
]
|
||||
asmDGProps [
|
||||
]
|
||||
bdDGProps [
|
||||
]
|
||||
syDGProps [
|
||||
]
|
||||
)
|
||||
(VersionControlTeamPreferences
|
||||
version "1.1"
|
||||
VMPlugin ""
|
||||
VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
|
||||
VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm"
|
||||
VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
|
||||
VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
|
||||
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
|
||||
VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
|
||||
VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
|
||||
VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
|
||||
VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
|
||||
VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
|
||||
VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
|
||||
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
|
||||
VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
|
||||
VMSvnHdlRepository ""
|
||||
VMDefaultView 1
|
||||
VMCurrentDesignHierarchyOnly 0
|
||||
VMUserData 1
|
||||
VMGeneratedHDL 0
|
||||
VMVerboseMode 0
|
||||
VMAlwaysEmpty 0
|
||||
VMSetTZ 1
|
||||
VMSymbol 1
|
||||
VMCurrentDesignHierarchy 0
|
||||
VMMultipleRepositoryMode 0
|
||||
VMSnapshotViewMode 0
|
||||
backupNameClashes 1
|
||||
clearCaseMaster 0
|
||||
)
|
||||
(CustomizeTeamPreferences
|
||||
version "1.1"
|
||||
FileTypes [
|
||||
]
|
||||
)
|
||||
]
|
||||
@ -1280,6 +1280,7 @@ projectPaths [
|
||||
"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\04-Lissajous\\Prefs\\hds.hdp"
|
||||
"C:\\work\\edu\\sem\\labo\\sem_labs\\04-Lissajous\\Prefs\\hds.hdp"
|
||||
"C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\hds.hdp"
|
||||
"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\zz-solutions\\04-Lissajous\\Prefs\\hds.hdp"
|
||||
]
|
||||
libMappingsRootDir ""
|
||||
teamLibMappingsRootDir ""
|
||||
@ -1300,289 +1301,67 @@ exportedDirectories [
|
||||
exportStdIncludeRefs 1
|
||||
exportStdPackageRefs 1
|
||||
)
|
||||
printerName "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN"
|
||||
printerName "Microsoft Print to PDF"
|
||||
pageSizes [
|
||||
(PageSizeInfo
|
||||
name "12\" x 18\""
|
||||
type 512
|
||||
width 1106
|
||||
height 1658
|
||||
name "Letter"
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "11\" x 17\""
|
||||
type 17
|
||||
name "Tabloid"
|
||||
type 3
|
||||
width 1013
|
||||
height 1566
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Legal (8,5\" x 14\")"
|
||||
name "Legal"
|
||||
type 5
|
||||
width 783
|
||||
height 1290
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Letter (8,5\" x 11\")"
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Executive (7,25\"x10,5\")"
|
||||
type 7
|
||||
width 667
|
||||
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|
||||
)
|
||||
(PageSizeInfo
|
||||
name "5,5\" x 8,5\""
|
||||
name "Statement"
|
||||
type 6
|
||||
width 506
|
||||
height 783
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "A3 (297 x 420 mm)"
|
||||
name "Executive"
|
||||
type 7
|
||||
width 667
|
||||
height 967
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "A3"
|
||||
type 8
|
||||
width 1077
|
||||
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|
||||
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||||
(PageSizeInfo
|
||||
name "A4 (210 x 297 mm)"
|
||||
name "A4"
|
||||
type 9
|
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width 761
|
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|
||||
)
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||||
(PageSizeInfo
|
||||
name "A5 (148 x 210 mm)"
|
||||
name "A5"
|
||||
type 11
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||||
width 538
|
||||
width 536
|
||||
height 761
|
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||||
(PageSizeInfo
|
||||
name "A6 (105 x 148 mm)"
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type 70
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||||
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|
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|
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||||
(PageSizeInfo
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||||
name "B4 JIS (257 x 364 mm)"
|
||||
name "B4 (JIS)"
|
||||
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||||
width 932
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||||
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|
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)
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(PageSizeInfo
|
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name "B5 JIS (182 x 257 mm)"
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name "B5 (JIS)"
|
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type 13
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(PageSizeInfo
|
||||
name "B6 JIS (128 x 182 mm)"
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(PageSizeInfo
|
||||
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|
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width 737
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(PageSizeInfo
|
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|
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|
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||||
(PageSizeInfo
|
||||
name "8,5\" x 13\""
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||||
type 14
|
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width 783
|
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|
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)
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||||
(PageSizeInfo
|
||||
name "8.5\" x 13.4\""
|
||||
type 551
|
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|
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)
|
||||
(PageSizeInfo
|
||||
name "Com10 Env.(4,125\"x9,5\")"
|
||||
type 20
|
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width 380
|
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|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Env.Monar.(3,875\"x7,5\")"
|
||||
type 37
|
||||
width 357
|
||||
height 691
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Env. DL (110 x 220 mm)"
|
||||
type 27
|
||||
width 399
|
||||
height 798
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Env. C6 (114 x 162 mm)"
|
||||
type 31
|
||||
width 413
|
||||
height 587
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Env. C5 (162 x 229 mm)"
|
||||
type 28
|
||||
width 587
|
||||
height 830
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "8K (267 x 390 mm)"
|
||||
type 520
|
||||
width 968
|
||||
height 1415
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "16K (195 x 267 mm)"
|
||||
type 521
|
||||
width 707
|
||||
height 968
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "8,25\" x 14\""
|
||||
type 522
|
||||
width 760
|
||||
height 1290
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "11\" x 14\""
|
||||
type 524
|
||||
width 1013
|
||||
height 1290
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "13\" x 19,2\""
|
||||
type 525
|
||||
width 1198
|
||||
height 1769
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "13\" x 19\""
|
||||
type 526
|
||||
width 1198
|
||||
height 1751
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "12,6\" x 19,2\""
|
||||
type 527
|
||||
width 1161
|
||||
height 1769
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "12,6\" x 18,5\""
|
||||
type 528
|
||||
width 1161
|
||||
height 1704
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "13\" x 18\""
|
||||
type 529
|
||||
width 1198
|
||||
height 1658
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "10\" x 14\""
|
||||
type 16
|
||||
width 921
|
||||
height 1290
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "10\" x 15\""
|
||||
type 546
|
||||
width 921
|
||||
height 1382
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "11\" x 15\""
|
||||
type 539
|
||||
width 1013
|
||||
height 1382
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "SRA3 (320 x 450 mm)"
|
||||
type 530
|
||||
width 1161
|
||||
height 1632
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "SRA4 (225 x 320 mm)"
|
||||
type 531
|
||||
width 816
|
||||
height 1161
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Format papier personnalis<69>"
|
||||
type 256
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size1(215,9 x 279,4 mm)"
|
||||
type 257
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size2(215,9 x 279,4 mm)"
|
||||
type 258
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size3(215,9 x 279,4 mm)"
|
||||
type 259
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size4(215,9 x 279,4 mm)"
|
||||
type 260
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size5(215,9 x 279,4 mm)"
|
||||
type 261
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size6(215,9 x 279,4 mm)"
|
||||
type 262
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size7(215,9 x 279,4 mm)"
|
||||
type 263
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size8(215,9 x 279,4 mm)"
|
||||
type 264
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size9(215,9 x 279,4 mm)"
|
||||
type 265
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
(PageSizeInfo
|
||||
name "Custom Paper Size10(215,9 x 279,4 mm)"
|
||||
type 266
|
||||
width 783
|
||||
height 1013
|
||||
)
|
||||
]
|
||||
exportPageSetupInfo (PageSetupInfo
|
||||
ptrCmd "FrameMaker MIF"
|
||||
@ -4292,7 +4071,7 @@ hdsWorkspaceLocation ""
|
||||
relativeLibraryRootDir ""
|
||||
vmLabelLatestDontAskAgain 0
|
||||
vmLabelWorkspaceDontAskAgain 0
|
||||
logWindowGeometry "600x619+-1073+193"
|
||||
logWindowGeometry "600x619+255+144"
|
||||
diagramBrowserTabNo 0
|
||||
showInsertPortHint 0
|
||||
showContentFirstTime 0
|
||||
|
||||
6710
zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/hds_user_prefs.bak
Normal file
6710
zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/hds_user_prefs.bak
Normal file
File diff suppressed because it is too large
Load Diff
@ -16,8 +16,8 @@ set VERBOSE=1
|
||||
set REQUIRE_LIBS=0
|
||||
set REQUIRE_HDS=1
|
||||
set REQUIRE_MODELSIM=1
|
||||
set REQUIRE_ISE=0
|
||||
set REQUIRE_DIAMOND=1
|
||||
set REQUIRE_ISE=1
|
||||
set REQUIRE_DIAMOND=0
|
||||
|
||||
:: Set project name
|
||||
set design_name=%~n0
|
||||
|
||||
Reference in New Issue
Block a user