Klagarge/SEm-Labos
Archived
1
0
Fork 0
Code Activity

add encoding SM --not finish yet

Browse Source
This commit is contained in:
Rémi Heredero
2024-04-10 14:22:10 +02:00
parent 7f4a0c615f
commit 8a64f5c04b
62 changed files with 19657 additions and 826 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
zz-solutions/04-Lissajous/Lissajous_test/hdl/lissajousgenerator_test_entity.vhg Normal file
View File

@ -0,0 +1,15 @@
-- VHDL Entity Lissajous_test.lissajousGenerator_test.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:07:27 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
ENTITY lissajousGenerator_test IS
-- Declarations
END lissajousGenerator_test ;

152
zz-solutions/04-Lissajous/Lissajous_test/hdl/lissajousgenerator_test_struct.vhg Normal file
View File

@ -0,0 +1,152 @@
--
-- VHDL Architecture Lissajous_test.lissajousGenerator_test.struct
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:48:46 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
LIBRARY Lissajous;
LIBRARY Lissajous_test;
LIBRARY WaveformGenerator;
ARCHITECTURE struct OF lissajousGenerator_test IS
-- Architecture declarations
constant signalBitNb: positive := 16;
constant phaseBitNb: positive := 17;
constant stepX: positive := 2;
constant stepY: positive := 3;
constant lowpassShiftBitNb: positive := 8;
constant clockFrequency: real := 60.0E6;
--constant clockFrequency: real := 66.0E6;
-- Internal signal declarations
SIGNAL clock : std_ulogic;
SIGNAL reset : std_ulogic;
SIGNAL triggerOut : std_ulogic;
SIGNAL xLowapss : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL xParallel : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL xSerial : std_ulogic;
SIGNAL yLowpass : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL yParallel : unsigned(signalBitNb-1 DOWNTO 0);
SIGNAL ySerial : std_ulogic;
-- Component Declarations
COMPONENT lissajousGenerator
GENERIC (
signalBitNb : positive := 16;
phaseBitNb : positive := 16;
stepX : positive := 1;
stepY : positive := 1
);
PORT (
clock : IN std_ulogic ;
reset : IN std_ulogic ;
triggerOut : OUT std_ulogic ;
xOut : OUT std_ulogic ;
yOut : OUT std_ulogic
);
END COMPONENT;
COMPONENT lissajousGenerator_tester
GENERIC (
signalBitNb : positive := 16;
clockFrequency : real := 60.0E6
);
PORT (
triggerOut : IN std_ulogic ;
xLowapss : IN unsigned (signalBitNb-1 DOWNTO 0);
xSerial : IN std_ulogic ;
yLowpass : IN unsigned (signalBitNb-1 DOWNTO 0);
ySerial : IN std_ulogic ;
clock : OUT std_ulogic ;
reset : OUT std_ulogic
);
END COMPONENT;
COMPONENT lowpass
GENERIC (
signalBitNb : positive := 16;
shiftBitNb : positive := 12
);
PORT (
lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0);
clock : IN std_ulogic ;
reset : IN std_ulogic ;
lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
FOR ALL : lissajousGenerator_tester USE ENTITY Lissajous_test.lissajousGenerator_tester;
FOR ALL : lowpass USE ENTITY WaveformGenerator.lowpass;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
xParallel <= (others => xSerial);
yParallel <= (others => ySerial);
-- Instance port mappings.
I_DUT : lissajousGenerator
GENERIC MAP (
signalBitNb => signalBitNb,
phaseBitNb => phaseBitNb,
stepX => stepX,
stepY => stepY
)
PORT MAP (
clock => clock,
reset => reset,
triggerOut => triggerOut,
xOut => xSerial,
yOut => ySerial
);
I_tester : lissajousGenerator_tester
GENERIC MAP (
signalBitNb => signalBitNb,
clockFrequency => clockFrequency
)
PORT MAP (
triggerOut => triggerOut,
xLowapss => xLowapss,
xSerial => xSerial,
yLowpass => yLowpass,
ySerial => ySerial,
clock => clock,
reset => reset
);
I_filtX : lowpass
GENERIC MAP (
signalBitNb => signalBitNb,
shiftBitNb => lowpassShiftBitNb
)
PORT MAP (
lowpassOut => xLowapss,
clock => clock,
reset => reset,
lowpassIn => xParallel
);
I_filty : lowpass
GENERIC MAP (
signalBitNb => signalBitNb,
shiftBitNb => lowpassShiftBitNb
)
PORT MAP (
lowpassOut => yLowpass,
clock => clock,
reset => reset,
lowpassIn => yParallel
);
END struct;

31
zz-solutions/04-Lissajous/Lissajous_test/hdl/lissajousgenerator_tester_entity.vhg Normal file
View File

@ -0,0 +1,31 @@
-- VHDL Entity Lissajous_test.lissajousGenerator_tester.interface
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:48:11 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
ENTITY lissajousGenerator_tester IS
GENERIC(
signalBitNb : positive := 16;
clockFrequency : real := 60.0E6
);
PORT(
triggerOut : IN std_ulogic;
xLowapss : IN unsigned (signalBitNb-1 DOWNTO 0);
xSerial : IN std_ulogic;
yLowpass : IN unsigned (signalBitNb-1 DOWNTO 0);
ySerial : IN std_ulogic;
clock : OUT std_ulogic;
reset : OUT std_ulogic
);
-- Declarations
END lissajousGenerator_tester ;

BIN
zz-solutions/04-Lissajous/Lissajous_test/hds/.cache.dat Normal file
View File

Binary file not shown.

12
zz-solutions/04-Lissajous/Lissajous_test/hds/.xrf/lissajousgenerator_test_entity.xrf Normal file
View File

@ -0,0 +1,12 @@
DESIGN lissajous@generator_test
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN lissajous@generator_test
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN lissajous@generator_test
VIEW symbol.sb
GRAPHIC 1,0 11 0
DESIGN lissajous@generator_test
VIEW symbol.sb
GRAPHIC 1,0 12 0

211
zz-solutions/04-Lissajous/Lissajous_test/hds/.xrf/lissajousgenerator_test_struct.xrf Normal file
View File

@ -0,0 +1,211 @@
DESIGN lissajous@generator_test
VIEW struct.bd
NO_GRAPHIC 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 142,0 9 0
DESIGN lissajous@generator_test
VIEW struct.bd
NO_GRAPHIC 12
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 0,0 17 2
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1,0 20 0
DESIGN lissajous@generator_test
VIEW struct.bd
NO_GRAPHIC 20
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1562,0 29 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1554,0 30 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1827,0 31 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1695,0 32 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1697,0 33 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1693,0 34 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1744,0 35 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1762,0 36 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1683,0 37 0
DESIGN lissajous@generator_test
VIEW struct.bd
NO_GRAPHIC 38
DESIGN lissajous@generator_test
VIEW struct.bd
NO_GRAPHIC 39
LIBRARY Lissajous
DESIGN lissajous@generator
VIEW struct
GRAPHIC 1594,0 41 0
DESIGN lissajous@generator
VIEW symbol.sb
GRAPHIC 14,0 42 1
DESIGN lissajous@generator
VIEW symbol.sb
GRAPHIC 52,0 49 0
DESIGN lissajous@generator
VIEW symbol.sb
GRAPHIC 428,0 50 0
DESIGN lissajous@generator
VIEW symbol.sb
GRAPHIC 88,0 51 0
DESIGN lissajous@generator
VIEW symbol.sb
GRAPHIC 93,0 52 0
DESIGN lissajous@generator
VIEW symbol.sb
GRAPHIC 98,0 53 0
LIBRARY Lissajous_test
DESIGN lissajous@generator_tester
VIEW test
GRAPHIC 421,0 56 0
DESIGN lissajous@generator_tester
VIEW interface
GRAPHIC 14,0 57 1
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1829,0 62 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1665,0 63 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1687,0 64 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1738,0 65 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1637,0 66 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1564,0 67 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1556,0 68 0
LIBRARY WaveformGenerator
DESIGN lowpass
VIEW master@version
GRAPHIC 1612,0 71 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 14,0 72 1
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 57,0 77 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 52,0 78 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 76,0 79 0
DESIGN lowpass
VIEW symbol.sb
GRAPHIC 83,0 80 0
LIBRARY Lissajous_test
DESIGN lissajous@generator_test
VIEW struct.bd
NO_GRAPHIC 83
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1594,0 86 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 421,0 87 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1612,0 88 0
DESIGN lissajous@generator_test
VIEW struct.bd
NO_GRAPHIC 91
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1603,0 94 0
DESIGN lissajous@generator_test
VIEW struct.bd
NO_GRAPHIC 97
DESIGN lissajous@generator_test
VIEW struct.bd
NO_GRAPHIC 98
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1594,0 100 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1601,0 101 1
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1564,0 108 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1556,0 109 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1829,0 110 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1687,0 111 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1637,0 112 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 421,0 114 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 428,0 115 1
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1612,0 128 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1619,0 129 1
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1665,0 134 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1659,0 135 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1653,0 136 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1671,0 137 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1699,0 139 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1706,0 140 1
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1738,0 145 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1724,0 146 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1730,0 147 0
DESIGN lissajous@generator_test
VIEW struct.bd
GRAPHIC 1756,0 148 0
DESIGN lissajous@generator_test
VIEW struct.bd
NO_GRAPHIC 151

36
zz-solutions/04-Lissajous/Lissajous_test/hds/.xrf/lissajousgenerator_tester_entity.xrf Normal file
View File

@ -0,0 +1,36 @@
DESIGN lissajous@generator_tester
VIEW interface
NO_GRAPHIC 0
DESIGN lissajous@generator_tester
VIEW interface
GRAPHIC 50,0 8 0
DESIGN lissajous@generator_tester
VIEW interface
GRAPHIC 13,0 13 1
DESIGN lissajous@generator_tester
VIEW interface
GRAPHIC 659,0 18 0
DESIGN lissajous@generator_tester
VIEW interface
GRAPHIC 664,0 19 0
DESIGN lissajous@generator_tester
VIEW interface
GRAPHIC 669,0 20 0
DESIGN lissajous@generator_tester
VIEW interface
GRAPHIC 674,0 21 0
DESIGN lissajous@generator_tester
VIEW interface
GRAPHIC 679,0 22 0
DESIGN lissajous@generator_tester
VIEW interface
GRAPHIC 649,0 23 0
DESIGN lissajous@generator_tester
VIEW interface
GRAPHIC 654,0 24 0
DESIGN lissajous@generator_tester
VIEW interface
GRAPHIC 1,0 27 0
DESIGN lissajous@generator_tester
VIEW interface
GRAPHIC 1,0 28 0