add encoding SM --not finish yet
This commit is contained in:
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7f4a0c615f
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BIN
05-Morse/Board/hds/.cache.dat
Normal file
BIN
05-Morse/Board/hds/.cache.dat
Normal file
Binary file not shown.
@ -34,10 +34,13 @@ TYPE SENDING_STATE_TYPE IS (
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sendR4,
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sendR4,
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waitR4,
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waitR4,
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sendR5,
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sendR5,
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waitSpace,
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waitEndWord
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waitEndWord
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);
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);
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signal sending_current_state, sending_next_state : SENDING_STATE_TYPE;
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signal sending_current_state, sending_next_state : SENDING_STATE_TYPE;
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signal signSendRegisters, signRegistersSended: std_ulogic;
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BEGIN
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BEGIN
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- conditions for morse units
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-- conditions for morse units
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@ -77,6 +80,7 @@ BEGIN
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is7 <= '1' when std_match(unsigned(char), "011" & x"7") else '0'; -- 011 0111
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is7 <= '1' when std_match(unsigned(char), "011" & x"7") else '0'; -- 011 0111
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is8 <= '1' when std_match(unsigned(char), "011" & x"8") else '0'; -- 011 1000
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is8 <= '1' when std_match(unsigned(char), "011" & x"8") else '0'; -- 011 1000
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is9 <= '1' when std_match(unsigned(char), "011" & x"9") else '0'; -- 011 1001
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is9 <= '1' when std_match(unsigned(char), "011" & x"9") else '0'; -- 011 1001
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------------------------------------------------------------------------------
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process(reset, clock) begin
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process(reset, clock) begin
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if reset = '1' then
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if reset = '1' then
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@ -89,25 +93,33 @@ BEGIN
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end process;
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end process;
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process(general_current_state) begin
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process(reset, clock) begin
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case general_current_state is
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case general_current_state is
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when waitForChar =>
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when waitForChar =>
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register1 <= END_WORD;
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--report "General current state is wait for char" severity note;
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register2 <= END_WORD;
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register1 <= SPACE;
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register3 <= END_WORD;
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register2 <= SPACE;
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register4 <= END_WORD;
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register3 <= SPACE;
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register5 <= END_WORD;
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register4 <= SPACE;
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register5 <= SPACE;
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signSendRegisters <= '0';
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if charNotReady = '0' then
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if charNotReady = '0' then
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general_next_state <= storeChar;
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general_next_state <= storeChar;
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readChar <= '1';
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report "charReady" severity note;
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else
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else
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general_next_state <= waitForChar;
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general_next_state <= waitForChar;
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readChar <= '0';
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--report "charNotReady" severity note;
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end if;
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end if;
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when storeChar =>
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when storeChar =>
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report "General current state is store char" severity note;
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if isA then
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if isA then
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register1 <= SHORT;
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register1 <= SHORT;
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register2 <= LONG;
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register2 <= LONG;
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general_next_state <= sendRegisters;
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general_next_state <= sendRegisters;
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report "New char: A" severity note;
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elsif isB then
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elsif isB then
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register1 <= LONG;
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register1 <= LONG;
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register2 <= SHORT;
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register2 <= SHORT;
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@ -128,6 +140,7 @@ BEGIN
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elsif isE then
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elsif isE then
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register1 <= SHORT;
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register1 <= SHORT;
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general_next_state <= sendRegisters;
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general_next_state <= sendRegisters;
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report "New char: E" severity note;
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elsif isF then
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elsif isF then
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register1 <= SHORT;
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register1 <= SHORT;
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register2 <= SHORT;
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register2 <= SHORT;
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@ -149,6 +162,7 @@ BEGIN
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register1 <= SHORT;
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register1 <= SHORT;
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register2 <= SHORT;
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register2 <= SHORT;
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general_next_state <= sendRegisters;
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general_next_state <= sendRegisters;
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report "New char: I" severity note;
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elsif isJ then
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elsif isJ then
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register1 <= SHORT;
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register1 <= SHORT;
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register2 <= LONG;
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register2 <= LONG;
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@ -170,6 +184,7 @@ BEGIN
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register1 <= LONG;
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register1 <= LONG;
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register2 <= LONG;
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register2 <= LONG;
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general_next_state <= sendRegisters;
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general_next_state <= sendRegisters;
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report "New char: M" severity note;
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elsif isN then
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elsif isN then
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register1 <= LONG;
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register1 <= LONG;
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register2 <= SHORT;
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register2 <= SHORT;
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@ -204,6 +219,7 @@ BEGIN
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elsif isT then
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elsif isT then
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register1 <= LONG;
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register1 <= LONG;
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general_next_state <= sendRegisters;
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general_next_state <= sendRegisters;
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report "New char: T" severity note;
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elsif isU then
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elsif isU then
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register1 <= SHORT;
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register1 <= SHORT;
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register2 <= SHORT;
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register2 <= SHORT;
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@ -309,36 +325,202 @@ BEGIN
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register5 <= SHORT;
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register5 <= SHORT;
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general_next_state <= sendRegisters;
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general_next_state <= sendRegisters;
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else
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else
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register1 <= END_WORD;
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register1 <= SPACE;
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register2 <= END_WORD;
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register2 <= SPACE;
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register3 <= END_WORD;
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register3 <= SPACE;
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register4 <= END_WORD;
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register4 <= SPACE;
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register5 <= END_WORD;
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register5 <= SPACE;
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general_next_state <= storeChar;
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general_next_state <= storeChar;
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report "Char look not correct" severity warning;
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end if;
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end if;
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signSendRegisters <= '1';
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when sendRegisters =>
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when sendRegisters =>
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sending_next_state <= sendR1;
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--report "General current state is send registers" severity note;
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readChar <= '0';
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signSendRegisters <= '0';
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if signRegistersSended then
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general_next_state <= sended;
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report "Char is send" severity note;
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end if;
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when sended =>
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when sended =>
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register1 <= END_WORD;
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--report "General current state is sended" severity note;
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register2 <= END_WORD;
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general_next_state <= waitForChar;
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register3 <= END_WORD;
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register1 <= SPACE;
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register4 <= END_WORD;
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register2 <= SPACE;
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register5 <= END_WORD;
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register3 <= SPACE;
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register4 <= SPACE;
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register5 <= SPACE;
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WHEN OTHERS =>
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WHEN OTHERS =>
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report "General current state is BROKEN" severity warning;
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general_next_state <= waitForChar;
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general_next_state <= waitForChar;
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end case;
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end case;
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end process;
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end process;
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process(sending_current_state) begin
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process(reset, clock) begin
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case sending_current_state is
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when waiting =>
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morseOut <= '0';
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startCounter <= '0';
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unitNb <= "000";
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signRegistersSended <= '0';
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if signSendRegisters = '1' then
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sending_next_state <= sendR1;
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report "Start to send new char" severity note;
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else
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sending_next_state <= waiting;
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end if;
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when sendR1 =>
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report "Send register1" severity note;
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startCounter <= '1';
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morseOut <= '1';
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case register1 is
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when SHORT =>
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unitNb <= "001";
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when LONG =>
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unitNb <= "011";
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when others =>
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report "Error when sending register1" severity error;
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end case;
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case register2 is
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when SPACE =>
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sending_next_state <= waitSpace;
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when END_WORD =>
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sending_next_state <= waitEndWord;
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when others =>
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sending_next_state <= waitR1;
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end case;
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when waitR1 =>
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report "Wait register1" severity note;
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startCounter <= '0';
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if counterDone = '1' then
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morseOut <= '0';
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sending_next_state <= sendR2;
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end if;
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when sendR2 =>
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report "Send register2" severity note;
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startCounter <= '1';
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morseOut <= '1';
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case register2 is
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when SHORT =>
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unitNb <= "001";
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when LONG =>
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unitNb <= "011";
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when others =>
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report "Error when sending register2" severity error;
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end case;
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case register3 is
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when SPACE =>
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sending_next_state <= waitSpace;
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when END_WORD =>
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sending_next_state <= waitEndWord;
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when others =>
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sending_next_state <= waitR2;
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end case;
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when waitR2 =>
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report "Wait register2" severity note;
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startCounter <= '0';
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if counterDone = '1' then
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morseOut <= '0';
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sending_next_state <= sendR3;
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end if;
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when sendR3 =>
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report "Send register3" severity note;
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startCounter <= '1';
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morseOut <= '1';
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case register3 is
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when SHORT =>
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unitNb <= "001";
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when LONG =>
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unitNb <= "011";
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when others =>
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report "Error when sending register3" severity error;
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end case;
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case register4 is
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when SPACE =>
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sending_next_state <= waitSpace;
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when END_WORD =>
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sending_next_state <= waitEndWord;
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when others =>
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sending_next_state <= waitR3;
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end case;
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when waitR3 =>
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startCounter <= '0';
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if counterDone = '1' then
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morseOut <= '0';
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sending_next_state <= sendR4;
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end if;
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when sendR4 =>
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startCounter <= '1';
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morseOut <= '1';
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case register4 is
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when SHORT =>
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unitNb <= "001";
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when LONG =>
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unitNb <= "011";
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when others =>
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report "Error when sending register4" severity error;
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end case;
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case register5 is
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when SPACE =>
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sending_next_state <= waitSpace;
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when END_WORD =>
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sending_next_state <= waitEndWord;
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when others =>
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sending_next_state <= waitR4;
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end case;
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when waitR4 =>
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startCounter <= '0';
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if counterDone = '1' then
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morseOut <= '0';
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sending_next_state <= sendR5;
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end if;
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when sendR5 =>
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startCounter <= '1';
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morseOut <= '1';
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case register5 is
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when SHORT =>
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unitNb <= "001";
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when LONG =>
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unitNb <= "011";
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when others =>
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report "Error when sending register5" severity error;
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end case;
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sending_next_state <= waitSpace;
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when waitSpace =>
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startCounter <= '0';
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if counterDone = '1' then
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morseOut <= '0';
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sending_next_state <= waiting;
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end if;
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signRegistersSended <= '1';
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when waitEndWord =>
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sending_next_state <= waiting;
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when others =>
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sending_next_state <= waiting;
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end case;
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end process;
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end process;
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morseOut <= '0';
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startCounter <= '0';
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unitNb <= (others => '-');
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END ARCHITECTURE studentVersion;
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END ARCHITECTURE studentVersion;
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@ -1,8 +1,8 @@
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-- VHDL Entity Morse.charToMorse.symbol
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-- VHDL Entity Morse.charToMorse.symbol
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--
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--
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-- Created:
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- by - remi.heredero.UNKNOWN (WE2330808)
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-- at - 14:49:52 28.04.2023
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-- at - 13:09:12 10.04.2024
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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--
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@ -2,8 +2,8 @@
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-- VHDL Architecture Morse.charToMorse.struct
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-- VHDL Architecture Morse.charToMorse.struct
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--
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--
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-- Created:
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- by - remi.heredero.UNKNOWN (WE2330808)
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-- at - 14:49:52 28.04.2023
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-- at - 13:09:12 10.04.2024
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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--
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BIN
05-Morse/Morse/hds/.cache.dat
Normal file
BIN
05-Morse/Morse/hds/.cache.dat
Normal file
Binary file not shown.
@ -64,23 +64,23 @@ VExpander (VariableExpander
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vvMap [
|
vvMap [
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(vvPair
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(vvPair
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variable "HDLDir"
|
variable "HDLDir"
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value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hdl"
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value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hdl"
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)
|
)
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(vvPair
|
(vvPair
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variable "HDSDir"
|
variable "HDSDir"
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value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds"
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)
|
)
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(vvPair
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(vvPair
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variable "SideDataDesignDir"
|
variable "SideDataDesignDir"
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value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\struct.bd.info"
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value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\struct.bd.info"
|
||||||
)
|
)
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||||||
(vvPair
|
(vvPair
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variable "SideDataUserDir"
|
variable "SideDataUserDir"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\struct.bd.user"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\struct.bd.user"
|
||||||
)
|
)
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||||||
(vvPair
|
(vvPair
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variable "SourceDir"
|
variable "SourceDir"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds"
|
||||||
)
|
)
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||||||
(vvPair
|
(vvPair
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||||||
variable "appl"
|
variable "appl"
|
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@ -104,27 +104,27 @@ value "%(unit)_%(view)_config"
|
|||||||
)
|
)
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||||||
(vvPair
|
(vvPair
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variable "d"
|
variable "d"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse"
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value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "d_logical"
|
variable "d_logical"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\charToMorse"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\charToMorse"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "date"
|
variable "date"
|
||||||
value "28.04.2023"
|
value "10.04.2024"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "day"
|
variable "day"
|
||||||
value "ven."
|
value "mer."
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "day_long"
|
variable "day_long"
|
||||||
value "vendredi"
|
value "mercredi"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "dd"
|
variable "dd"
|
||||||
value "28"
|
value "10"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "designName"
|
variable "designName"
|
||||||
@ -152,11 +152,11 @@ value "struct"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_author"
|
variable "graphical_source_author"
|
||||||
value "axel.amand"
|
value "remi.heredero"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_date"
|
variable "graphical_source_date"
|
||||||
value "28.04.2023"
|
value "10.04.2024"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_group"
|
variable "graphical_source_group"
|
||||||
@ -164,11 +164,11 @@ value "UNKNOWN"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_host"
|
variable "graphical_source_host"
|
||||||
value "WE7860"
|
value "WE2330808"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_time"
|
variable "graphical_source_time"
|
||||||
value "14:49:52"
|
value "13:09:12"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "group"
|
variable "group"
|
||||||
@ -176,7 +176,7 @@ value "UNKNOWN"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "host"
|
variable "host"
|
||||||
value "WE7860"
|
value "WE2330808"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "language"
|
variable "language"
|
||||||
@ -187,6 +187,10 @@ variable "library"
|
|||||||
value "Morse"
|
value "Morse"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
|
variable "library_downstream_Concatenation"
|
||||||
|
value "$HDS_PROJECT_DIR/../Morse/concat"
|
||||||
|
)
|
||||||
|
(vvPair
|
||||||
variable "library_downstream_ModelSimCompiler"
|
variable "library_downstream_ModelSimCompiler"
|
||||||
value "$SCRATCH_DIR/Morse"
|
value "$SCRATCH_DIR/Morse"
|
||||||
)
|
)
|
||||||
@ -208,11 +212,11 @@ value "avril"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "p"
|
variable "p"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\struct.bd"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\struct.bd"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "p_logical"
|
variable "p_logical"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\charToMorse\\struct.bd"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\charToMorse\\struct.bd"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "package_name"
|
variable "package_name"
|
||||||
@ -264,7 +268,7 @@ value "struct"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "time"
|
variable "time"
|
||||||
value "14:49:52"
|
value "13:09:12"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "unit"
|
variable "unit"
|
||||||
@ -272,7 +276,7 @@ value "charToMorse"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "user"
|
variable "user"
|
||||||
value "axel.amand"
|
value "remi.heredero"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "version"
|
variable "version"
|
||||||
@ -284,11 +288,11 @@ value "struct"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "year"
|
variable "year"
|
||||||
value "2023"
|
value "2024"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "yy"
|
variable "yy"
|
||||||
value "23"
|
value "24"
|
||||||
)
|
)
|
||||||
]
|
]
|
||||||
)
|
)
|
||||||
@ -1692,7 +1696,7 @@ text (MLText
|
|||||||
uid 814,0
|
uid 814,0
|
||||||
va (VaSet
|
va (VaSet
|
||||||
)
|
)
|
||||||
xt "15000,42600,41700,45000"
|
xt "12000,42600,38700,45000"
|
||||||
st "characterBitNb = characterBitNb ( positive )
|
st "characterBitNb = characterBitNb ( positive )
|
||||||
unitCountBitNb = unitCountBitNb ( positive ) "
|
unitCountBitNb = unitCountBitNb ( positive ) "
|
||||||
)
|
)
|
||||||
@ -1906,9 +1910,9 @@ f (Text
|
|||||||
uid 370,0
|
uid 370,0
|
||||||
va (VaSet
|
va (VaSet
|
||||||
)
|
)
|
||||||
xt "33750,30000,41550,31200"
|
xt "34000,29800,41800,31000"
|
||||||
st "startCounter"
|
st "startCounter"
|
||||||
blo "33750,31000"
|
blo "34000,30800"
|
||||||
tm "WireNameMgr"
|
tm "WireNameMgr"
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
@ -1986,9 +1990,9 @@ f (Text
|
|||||||
uid 382,0
|
uid 382,0
|
||||||
va (VaSet
|
va (VaSet
|
||||||
)
|
)
|
||||||
xt "33750,32000,37750,33200"
|
xt "34000,31800,38000,33000"
|
||||||
st "unitNb"
|
st "unitNb"
|
||||||
blo "33750,33000"
|
blo "34000,32800"
|
||||||
tm "WireNameMgr"
|
tm "WireNameMgr"
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
@ -2246,8 +2250,8 @@ tm "BdCompilerDirectivesTextMgr"
|
|||||||
]
|
]
|
||||||
associable 1
|
associable 1
|
||||||
)
|
)
|
||||||
windowSize "-8,-8,1928,1048"
|
windowSize "301,100,1557,827"
|
||||||
viewArea "-8435,-1430,118740,67667"
|
viewArea "-750,11425,76350,54400"
|
||||||
cachedDiagramExtent "-7000,0,90000,66000"
|
cachedDiagramExtent "-7000,0,90000,66000"
|
||||||
pageSetupInfo (PageSetupInfo
|
pageSetupInfo (PageSetupInfo
|
||||||
ptrCmd ""
|
ptrCmd ""
|
||||||
@ -2274,7 +2278,7 @@ exportStdPackageRefs 1
|
|||||||
)
|
)
|
||||||
hasePageBreakOrigin 1
|
hasePageBreakOrigin 1
|
||||||
pageBreakOrigin "-7000,0"
|
pageBreakOrigin "-7000,0"
|
||||||
lastUid 923,0
|
lastUid 950,0
|
||||||
defaultCommentText (CommentText
|
defaultCommentText (CommentText
|
||||||
shape (Rectangle
|
shape (Rectangle
|
||||||
layer 0
|
layer 0
|
||||||
|
|||||||
3809
05-Morse/Morse/hds/char@to@morse/struct.bd.bak
Normal file
3809
05-Morse/Morse/hds/char@to@morse/struct.bd.bak
Normal file
File diff suppressed because it is too large
Load Diff
@ -477,23 +477,23 @@ value " "
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "HDLDir"
|
variable "HDLDir"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hdl"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hdl"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "HDSDir"
|
variable "HDSDir"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "SideDataDesignDir"
|
variable "SideDataDesignDir"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\symbol.sb.info"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\symbol.sb.info"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "SideDataUserDir"
|
variable "SideDataUserDir"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\symbol.sb.user"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\symbol.sb.user"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "SourceDir"
|
variable "SourceDir"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "appl"
|
variable "appl"
|
||||||
@ -517,27 +517,27 @@ value "%(unit)_%(view)_config"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "d"
|
variable "d"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "d_logical"
|
variable "d_logical"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\charToMorse"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\charToMorse"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "date"
|
variable "date"
|
||||||
value "28.04.2023"
|
value "10.04.2024"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "day"
|
variable "day"
|
||||||
value "ven."
|
value "mer."
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "day_long"
|
variable "day_long"
|
||||||
value "vendredi"
|
value "mercredi"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "dd"
|
variable "dd"
|
||||||
value "28"
|
value "10"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "designName"
|
variable "designName"
|
||||||
@ -565,11 +565,11 @@ value "symbol"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_author"
|
variable "graphical_source_author"
|
||||||
value "axel.amand"
|
value "remi.heredero"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_date"
|
variable "graphical_source_date"
|
||||||
value "28.04.2023"
|
value "10.04.2024"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_group"
|
variable "graphical_source_group"
|
||||||
@ -577,11 +577,11 @@ value "UNKNOWN"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_host"
|
variable "graphical_source_host"
|
||||||
value "WE7860"
|
value "WE2330808"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "graphical_source_time"
|
variable "graphical_source_time"
|
||||||
value "14:49:52"
|
value "13:09:12"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "group"
|
variable "group"
|
||||||
@ -589,7 +589,7 @@ value "UNKNOWN"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "host"
|
variable "host"
|
||||||
value "WE7860"
|
value "WE2330808"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "language"
|
variable "language"
|
||||||
@ -600,6 +600,10 @@ variable "library"
|
|||||||
value "Morse"
|
value "Morse"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
|
variable "library_downstream_Concatenation"
|
||||||
|
value "$HDS_PROJECT_DIR/../Morse/concat"
|
||||||
|
)
|
||||||
|
(vvPair
|
||||||
variable "library_downstream_Generic_1_file"
|
variable "library_downstream_Generic_1_file"
|
||||||
value "U:\\SEm_curves\\Synthesis"
|
value "U:\\SEm_curves\\Synthesis"
|
||||||
)
|
)
|
||||||
@ -633,11 +637,11 @@ value "avril"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "p"
|
variable "p"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\symbol.sb"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\symbol.sb"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "p_logical"
|
variable "p_logical"
|
||||||
value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\charToMorse\\symbol.sb"
|
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\charToMorse\\symbol.sb"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "package_name"
|
variable "package_name"
|
||||||
@ -713,7 +717,7 @@ value "symbol"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "time"
|
variable "time"
|
||||||
value "14:49:52"
|
value "13:09:12"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "unit"
|
variable "unit"
|
||||||
@ -721,7 +725,7 @@ value "charToMorse"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "user"
|
variable "user"
|
||||||
value "axel.amand"
|
value "remi.heredero"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "version"
|
variable "version"
|
||||||
@ -733,11 +737,11 @@ value "symbol"
|
|||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "year"
|
variable "year"
|
||||||
value "2023"
|
value "2024"
|
||||||
)
|
)
|
||||||
(vvPair
|
(vvPair
|
||||||
variable "yy"
|
variable "yy"
|
||||||
value "23"
|
value "24"
|
||||||
)
|
)
|
||||||
]
|
]
|
||||||
)
|
)
|
||||||
@ -1715,7 +1719,7 @@ xt "0,6000,0,6000"
|
|||||||
tm "SyDeclarativeTextMgr"
|
tm "SyDeclarativeTextMgr"
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
lastUid 818,0
|
lastUid 841,0
|
||||||
okToSyncOnLoad 1
|
okToSyncOnLoad 1
|
||||||
OkToSyncGenericsOnLoad 1
|
OkToSyncGenericsOnLoad 1
|
||||||
activeModelName "Symbol"
|
activeModelName "Symbol"
|
||||||
|
|||||||
BIN
05-Morse/Morse_test/hds/.cache.dat
Normal file
BIN
05-Morse/Morse_test/hds/.cache.dat
Normal file
Binary file not shown.
@ -6249,7 +6249,7 @@ yPos 0
|
|||||||
width 1936
|
width 1936
|
||||||
height 1056
|
height 1056
|
||||||
activeSidePanelTab 2
|
activeSidePanelTab 2
|
||||||
activeLibraryTab 2
|
activeLibraryTab 3
|
||||||
sidePanelSize 278
|
sidePanelSize 278
|
||||||
showUnixHiddenFiles 0
|
showUnixHiddenFiles 0
|
||||||
componentBrowserXpos 569
|
componentBrowserXpos 569
|
||||||
|
|||||||
@ -2796,7 +2796,7 @@ second ""
|
|||||||
)
|
)
|
||||||
(pair
|
(pair
|
||||||
first "hierLevel"
|
first "hierLevel"
|
||||||
second "1"
|
second "3"
|
||||||
)
|
)
|
||||||
(pair
|
(pair
|
||||||
first "onPulldownMenu"
|
first "onPulldownMenu"
|
||||||
|
|||||||
BIN
Libs/Common/hds/.cache.dat
Normal file
BIN
Libs/Common/hds/.cache.dat
Normal file
Binary file not shown.
BIN
Libs/Common_test/hds/.cache.dat
Normal file
BIN
Libs/Common_test/hds/.cache.dat
Normal file
Binary file not shown.
BIN
Libs/Lattice/hds/.cache.dat
Normal file
BIN
Libs/Lattice/hds/.cache.dat
Normal file
Binary file not shown.
32
Libs/Memory/hdl/fifo_bram_entity.vhg
Normal file
32
Libs/Memory/hdl/fifo_bram_entity.vhg
Normal file
@ -0,0 +1,32 @@
|
|||||||
|
-- VHDL Entity Memory.FIFO_bram.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - francois.francois (Aphelia)
|
||||||
|
-- at - 13:45:15 08/28/19
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
ENTITY FIFO_bram IS
|
||||||
|
GENERIC(
|
||||||
|
dataBitNb : positive := 8;
|
||||||
|
depth : positive := 8
|
||||||
|
);
|
||||||
|
PORT(
|
||||||
|
write : IN std_ulogic;
|
||||||
|
clock : IN std_ulogic;
|
||||||
|
reset : IN std_ulogic;
|
||||||
|
dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0);
|
||||||
|
read : IN std_ulogic;
|
||||||
|
dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0);
|
||||||
|
empty : OUT std_ulogic;
|
||||||
|
full : OUT std_ulogic
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END FIFO_bram ;
|
||||||
|
|
||||||
BIN
Libs/Memory/hds/.cache.dat
Normal file
BIN
Libs/Memory/hds/.cache.dat
Normal file
Binary file not shown.
39
Libs/Memory/hds/.xrf/fifo_bram_entity.xrf
Normal file
39
Libs/Memory/hds/.xrf/fifo_bram_entity.xrf
Normal file
@ -0,0 +1,39 @@
|
|||||||
|
DESIGN @f@i@f@o_bram
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN @f@i@f@o_bram
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 50,0 8 0
|
||||||
|
DESIGN @f@i@f@o_bram
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 13,0 13 1
|
||||||
|
DESIGN @f@i@f@o_bram
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 168,0 18 0
|
||||||
|
DESIGN @f@i@f@o_bram
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 173,0 19 0
|
||||||
|
DESIGN @f@i@f@o_bram
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 178,0 20 0
|
||||||
|
DESIGN @f@i@f@o_bram
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 188,0 21 0
|
||||||
|
DESIGN @f@i@f@o_bram
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 193,0 22 0
|
||||||
|
DESIGN @f@i@f@o_bram
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 216,0 23 0
|
||||||
|
DESIGN @f@i@f@o_bram
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 221,0 24 0
|
||||||
|
DESIGN @f@i@f@o_bram
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 229,0 25 0
|
||||||
|
DESIGN @f@i@f@o_bram
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 28 0
|
||||||
|
DESIGN @f@i@f@o_bram
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 29 0
|
||||||
29
Libs/RS232/hdl/serialportreceiver_entity.vhg
Normal file
29
Libs/RS232/hdl/serialportreceiver_entity.vhg
Normal file
@ -0,0 +1,29 @@
|
|||||||
|
-- VHDL Entity RS232.serialPortReceiver.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - francois.francois (Aphelia)
|
||||||
|
-- at - 13:45:48 08/28/19
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
ENTITY serialPortReceiver IS
|
||||||
|
GENERIC(
|
||||||
|
dataBitNb : positive := 8;
|
||||||
|
baudRateDivide : positive := 2083
|
||||||
|
);
|
||||||
|
PORT(
|
||||||
|
RxD : IN std_ulogic;
|
||||||
|
clock : IN std_ulogic;
|
||||||
|
reset : IN std_ulogic;
|
||||||
|
dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0);
|
||||||
|
dataValid : OUT std_ulogic
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END serialPortReceiver ;
|
||||||
|
|
||||||
BIN
Libs/RS232/hds/.cache.dat
Normal file
BIN
Libs/RS232/hds/.cache.dat
Normal file
Binary file not shown.
30
Libs/RS232/hds/.xrf/serialportreceiver_entity.xrf
Normal file
30
Libs/RS232/hds/.xrf/serialportreceiver_entity.xrf
Normal file
@ -0,0 +1,30 @@
|
|||||||
|
DESIGN serial@port@receiver
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN serial@port@receiver
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 50,0 8 0
|
||||||
|
DESIGN serial@port@receiver
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 13,0 13 1
|
||||||
|
DESIGN serial@port@receiver
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 168,0 18 0
|
||||||
|
DESIGN serial@port@receiver
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 173,0 19 0
|
||||||
|
DESIGN serial@port@receiver
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 178,0 20 0
|
||||||
|
DESIGN serial@port@receiver
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 188,0 21 0
|
||||||
|
DESIGN serial@port@receiver
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 193,0 22 0
|
||||||
|
DESIGN serial@port@receiver
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 25 0
|
||||||
|
DESIGN serial@port@receiver
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 26 0
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -0,0 +1,55 @@
|
|||||||
|
version "8.0"
|
||||||
|
RenoirTeamPreferences [
|
||||||
|
(BaseTeamPreferences
|
||||||
|
version "1.1"
|
||||||
|
verConcat 0
|
||||||
|
ttDGProps [
|
||||||
|
]
|
||||||
|
fcDGProps [
|
||||||
|
]
|
||||||
|
smDGProps [
|
||||||
|
]
|
||||||
|
asmDGProps [
|
||||||
|
]
|
||||||
|
bdDGProps [
|
||||||
|
]
|
||||||
|
syDGProps [
|
||||||
|
]
|
||||||
|
)
|
||||||
|
(VersionControlTeamPreferences
|
||||||
|
version "1.1"
|
||||||
|
VMPlugin ""
|
||||||
|
VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
|
||||||
|
VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm"
|
||||||
|
VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
|
||||||
|
VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
|
||||||
|
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
|
||||||
|
VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
|
||||||
|
VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
|
||||||
|
VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
|
||||||
|
VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
|
||||||
|
VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
|
||||||
|
VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
|
||||||
|
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
|
||||||
|
VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
|
||||||
|
VMSvnHdlRepository ""
|
||||||
|
VMDefaultView 1
|
||||||
|
VMCurrentDesignHierarchyOnly 0
|
||||||
|
VMUserData 1
|
||||||
|
VMGeneratedHDL 0
|
||||||
|
VMVerboseMode 0
|
||||||
|
VMAlwaysEmpty 0
|
||||||
|
VMSetTZ 1
|
||||||
|
VMSymbol 1
|
||||||
|
VMCurrentDesignHierarchy 0
|
||||||
|
VMMultipleRepositoryMode 0
|
||||||
|
VMSnapshotViewMode 0
|
||||||
|
backupNameClashes 1
|
||||||
|
clearCaseMaster 0
|
||||||
|
)
|
||||||
|
(CustomizeTeamPreferences
|
||||||
|
version "1.1"
|
||||||
|
FileTypes [
|
||||||
|
]
|
||||||
|
)
|
||||||
|
]
|
||||||
@ -1280,6 +1280,7 @@ projectPaths [
|
|||||||
"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\03-DigitalToAnalogConverter\\Prefs\\hds.hdp"
|
"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\03-DigitalToAnalogConverter\\Prefs\\hds.hdp"
|
||||||
"C:\\work\\edu\\sem\\labo\\sem_labs\\03-DigitalToAnalogConverter\\Prefs\\hds.hdp"
|
"C:\\work\\edu\\sem\\labo\\sem_labs\\03-DigitalToAnalogConverter\\Prefs\\hds.hdp"
|
||||||
"C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\hds.hdp"
|
"C:\\dev\\sem-labs\\03-DigitalToAnalogConverter\\Prefs\\hds.hdp"
|
||||||
|
"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\zz-solutions\\03-DigitalToAnalogConverter\\Prefs\\hds.hdp"
|
||||||
]
|
]
|
||||||
libMappingsRootDir ""
|
libMappingsRootDir ""
|
||||||
teamLibMappingsRootDir ""
|
teamLibMappingsRootDir ""
|
||||||
@ -1300,288 +1301,144 @@ exportedDirectories [
|
|||||||
exportStdIncludeRefs 1
|
exportStdIncludeRefs 1
|
||||||
exportStdPackageRefs 1
|
exportStdPackageRefs 1
|
||||||
)
|
)
|
||||||
printerName "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN"
|
printerName "\\\\vmenpprint1\\VS-ENP.23.N308-PRN"
|
||||||
pageSizes [
|
pageSizes [
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "12\" x 18\""
|
name "Letter"
|
||||||
type 512
|
width 783
|
||||||
width 1106
|
height 1013
|
||||||
height 1658
|
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "11\" x 17\""
|
name "Legal"
|
||||||
type 17
|
|
||||||
width 1013
|
|
||||||
height 1566
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Legal (8,5\" x 14\")"
|
|
||||||
type 5
|
type 5
|
||||||
width 783
|
width 783
|
||||||
height 1290
|
height 1290
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "Letter (8,5\" x 11\")"
|
name "Statement"
|
||||||
width 783
|
|
||||||
height 1013
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Executive (7,25\"x10,5\")"
|
|
||||||
type 7
|
|
||||||
width 667
|
|
||||||
height 967
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "5,5\" x 8,5\""
|
|
||||||
type 6
|
type 6
|
||||||
width 506
|
width 506
|
||||||
height 783
|
height 783
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "A3 (297 x 420 mm)"
|
name "Executive"
|
||||||
|
type 7
|
||||||
|
width 667
|
||||||
|
height 967
|
||||||
|
)
|
||||||
|
(PageSizeInfo
|
||||||
|
name "A3"
|
||||||
type 8
|
type 8
|
||||||
width 1077
|
width 1077
|
||||||
height 1523
|
height 1523
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "A4 (210 x 297 mm)"
|
name "A4"
|
||||||
type 9
|
type 9
|
||||||
width 761
|
width 761
|
||||||
height 1077
|
height 1077
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "A5 (148 x 210 mm)"
|
name "A5"
|
||||||
type 11
|
type 11
|
||||||
width 538
|
width 536
|
||||||
height 761
|
height 761
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "A6 (105 x 148 mm)"
|
name "B4 (JIS)"
|
||||||
type 70
|
|
||||||
width 380
|
|
||||||
height 538
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "B4 JIS (257 x 364 mm)"
|
|
||||||
type 12
|
type 12
|
||||||
width 932
|
width 932
|
||||||
height 1320
|
height 1320
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "B5 JIS (182 x 257 mm)"
|
name "B5 (JIS)"
|
||||||
type 13
|
type 13
|
||||||
width 660
|
width 660
|
||||||
height 932
|
height 932
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "B6 JIS (128 x 182 mm)"
|
name "11×17"
|
||||||
type 88
|
type 17
|
||||||
width 464
|
width 1013
|
||||||
height 660
|
height 1566
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "8\" x 13\""
|
name "Envelope #10"
|
||||||
type 518
|
|
||||||
width 737
|
|
||||||
height 1198
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "8,25\" x 13\""
|
|
||||||
type 519
|
|
||||||
width 760
|
|
||||||
height 1198
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "8,5\" x 13\""
|
|
||||||
type 14
|
|
||||||
width 783
|
|
||||||
height 1198
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "8.5\" x 13.4\""
|
|
||||||
type 551
|
|
||||||
width 783
|
|
||||||
height 1235
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Com10 Env.(4,125\"x9,5\")"
|
|
||||||
type 20
|
type 20
|
||||||
width 380
|
width 379
|
||||||
height 875
|
height 875
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "Env.Monar.(3,875\"x7,5\")"
|
name "Envelope DL"
|
||||||
type 37
|
|
||||||
width 357
|
|
||||||
height 691
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Env. DL (110 x 220 mm)"
|
|
||||||
type 27
|
type 27
|
||||||
width 399
|
width 399
|
||||||
height 798
|
height 798
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "Env. C6 (114 x 162 mm)"
|
name "Envelope C5"
|
||||||
type 31
|
|
||||||
width 413
|
|
||||||
height 587
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Env. C5 (162 x 229 mm)"
|
|
||||||
type 28
|
type 28
|
||||||
width 587
|
width 587
|
||||||
height 830
|
height 830
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "8K (267 x 390 mm)"
|
name "Envelope B5"
|
||||||
type 520
|
type 34
|
||||||
width 968
|
width 638
|
||||||
height 1415
|
height 907
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "16K (195 x 267 mm)"
|
name "Envelope Monarch"
|
||||||
type 521
|
type 37
|
||||||
width 707
|
width 357
|
||||||
height 968
|
height 691
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "8,25\" x 14\""
|
name "Japanese Postcard"
|
||||||
type 522
|
type 43
|
||||||
width 760
|
width 362
|
||||||
height 1290
|
height 536
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "11\" x 14\""
|
name "A6"
|
||||||
type 524
|
type 70
|
||||||
width 1013
|
width 380
|
||||||
height 1290
|
height 536
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "13\" x 19,2\""
|
name "Double Japan Postcard Rotated"
|
||||||
type 525
|
type 82
|
||||||
width 1198
|
width 536
|
||||||
height 1769
|
height 725
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "13\" x 19\""
|
name "Executive (JIS)"
|
||||||
type 526
|
type 119
|
||||||
width 1198
|
width 783
|
||||||
height 1751
|
height 1196
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "12,6\" x 19,2\""
|
name "Oficio 8.5x13"
|
||||||
type 527
|
type 120
|
||||||
width 1161
|
width 783
|
||||||
height 1769
|
height 1198
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "12,6\" x 18,5\""
|
name "12x18"
|
||||||
type 528
|
type 121
|
||||||
width 1161
|
width 1105
|
||||||
height 1704
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "13\" x 18\""
|
|
||||||
type 529
|
|
||||||
width 1198
|
|
||||||
height 1658
|
height 1658
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "10\" x 14\""
|
name "8K 273x394 mm"
|
||||||
type 16
|
type 139
|
||||||
width 921
|
width 990
|
||||||
height 1290
|
height 1428
|
||||||
)
|
)
|
||||||
(PageSizeInfo
|
(PageSizeInfo
|
||||||
name "10\" x 15\""
|
name "16K 197x273 mm"
|
||||||
type 546
|
type 140
|
||||||
width 921
|
width 714
|
||||||
height 1382
|
height 990
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "11\" x 15\""
|
|
||||||
type 539
|
|
||||||
width 1013
|
|
||||||
height 1382
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "SRA3 (320 x 450 mm)"
|
|
||||||
type 530
|
|
||||||
width 1161
|
|
||||||
height 1632
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "SRA4 (225 x 320 mm)"
|
|
||||||
type 531
|
|
||||||
width 816
|
|
||||||
height 1161
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Format papier personnalisé"
|
|
||||||
type 256
|
|
||||||
width 783
|
|
||||||
height 1013
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Custom Paper Size1(215,9 x 279,4 mm)"
|
|
||||||
type 257
|
|
||||||
width 783
|
|
||||||
height 1013
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Custom Paper Size2(215,9 x 279,4 mm)"
|
|
||||||
type 258
|
|
||||||
width 783
|
|
||||||
height 1013
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Custom Paper Size3(215,9 x 279,4 mm)"
|
|
||||||
type 259
|
|
||||||
width 783
|
|
||||||
height 1013
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Custom Paper Size4(215,9 x 279,4 mm)"
|
|
||||||
type 260
|
|
||||||
width 783
|
|
||||||
height 1013
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Custom Paper Size5(215,9 x 279,4 mm)"
|
|
||||||
type 261
|
|
||||||
width 783
|
|
||||||
height 1013
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Custom Paper Size6(215,9 x 279,4 mm)"
|
|
||||||
type 262
|
|
||||||
width 783
|
|
||||||
height 1013
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Custom Paper Size7(215,9 x 279,4 mm)"
|
|
||||||
type 263
|
|
||||||
width 783
|
|
||||||
height 1013
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Custom Paper Size8(215,9 x 279,4 mm)"
|
|
||||||
type 264
|
|
||||||
width 783
|
|
||||||
height 1013
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Custom Paper Size9(215,9 x 279,4 mm)"
|
|
||||||
type 265
|
|
||||||
width 783
|
|
||||||
height 1013
|
|
||||||
)
|
|
||||||
(PageSizeInfo
|
|
||||||
name "Custom Paper Size10(215,9 x 279,4 mm)"
|
|
||||||
type 266
|
|
||||||
width 783
|
|
||||||
height 1013
|
|
||||||
)
|
)
|
||||||
]
|
]
|
||||||
exportPageSetupInfo (PageSetupInfo
|
exportPageSetupInfo (PageSetupInfo
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@ -24,8 +24,8 @@ set design_name=%~n0
|
|||||||
::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries
|
::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries
|
||||||
|
|
||||||
::set HDS_HOME=C:\eda\MentorGraphics\HDS
|
::set HDS_HOME=C:\eda\MentorGraphics\HDS
|
||||||
set HDS_HOME=C:\MentorGraphics\HDS_2019.2
|
::set HDS_HOME=C:\MentorGraphics\HDS_2019.2
|
||||||
set MODELSIM_HOME=C:\modeltech64_2021.3\win64
|
::set MODELSIM_HOME=C:\modeltech64_2021.3\win64
|
||||||
::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64
|
::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64
|
||||||
::set ISE_VERSION=14.7
|
::set ISE_VERSION=14.7
|
||||||
::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE
|
::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE
|
||||||
|
|||||||
@ -1,8 +1,8 @@
|
|||||||
-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol
|
-- VHDL Entity Board.lissajousGenerator_circuit_EBS2.symbol
|
||||||
--
|
--
|
||||||
-- Created:
|
-- Created:
|
||||||
-- by - axel.amand.UNKNOWN (WE7860)
|
-- by - francois.francois (Aphelia)
|
||||||
-- at - 17:45:49 01.05.2023
|
-- at - 13:07:18 02/19/19
|
||||||
--
|
--
|
||||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
--
|
--
|
||||||
@ -10,7 +10,10 @@ LIBRARY ieee;
|
|||||||
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_1164.all;
|
||||||
USE ieee.numeric_std.all;
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
ENTITY lissajousGenerator_circuit_EBS3 IS
|
ENTITY lissajousGenerator_circuit_EBS2 IS
|
||||||
|
GENERIC(
|
||||||
|
bitNb : positive := 16
|
||||||
|
);
|
||||||
PORT(
|
PORT(
|
||||||
clock : IN std_ulogic;
|
clock : IN std_ulogic;
|
||||||
reset_N : IN std_ulogic;
|
reset_N : IN std_ulogic;
|
||||||
@ -21,7 +24,7 @@ ENTITY lissajousGenerator_circuit_EBS3 IS
|
|||||||
|
|
||||||
-- Declarations
|
-- Declarations
|
||||||
|
|
||||||
END lissajousGenerator_circuit_EBS3 ;
|
END lissajousGenerator_circuit_EBS2 ;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@ -1340,109 +1343,12 @@ END struct;
|
|||||||
|
|
||||||
|
|
||||||
|
|
||||||
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
|
|
||||||
-- Module Version: 5.7
|
|
||||||
--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc
|
|
||||||
|
|
||||||
-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks
|
|
||||||
|
|
||||||
library IEEE;
|
|
||||||
use IEEE.std_logic_1164.all;
|
|
||||||
library ECP5U;
|
|
||||||
use ECP5U.components.all;
|
|
||||||
|
|
||||||
ENTITY pll IS
|
|
||||||
PORT(
|
|
||||||
clkIn100M : IN std_ulogic;
|
|
||||||
en75M : IN std_ulogic;
|
|
||||||
en50M : IN std_ulogic;
|
|
||||||
en10M : IN std_ulogic;
|
|
||||||
clk60MHz : OUT std_ulogic;
|
|
||||||
clk75MHz : OUT std_ulogic;
|
|
||||||
clk50MHz : OUT std_ulogic;
|
|
||||||
clk10MHz : OUT std_ulogic;
|
|
||||||
pllLocked : OUT std_ulogic
|
|
||||||
);
|
|
||||||
|
|
||||||
-- Declarations
|
|
||||||
|
|
||||||
END pll ;
|
|
||||||
|
|
||||||
architecture rtl of pll is
|
|
||||||
|
|
||||||
-- internal signal declarations
|
|
||||||
signal REFCLK: std_logic;
|
|
||||||
signal CLKOS3_t: std_logic;
|
|
||||||
signal CLKOS2_t: std_logic;
|
|
||||||
signal CLKOS_t: std_logic;
|
|
||||||
signal CLKOP_t: std_logic;
|
|
||||||
signal scuba_vhi: std_logic;
|
|
||||||
signal scuba_vlo: std_logic;
|
|
||||||
|
|
||||||
attribute FREQUENCY_PIN_CLKOS3 : string;
|
|
||||||
attribute FREQUENCY_PIN_CLKOS2 : string;
|
|
||||||
attribute FREQUENCY_PIN_CLKOS : string;
|
|
||||||
attribute FREQUENCY_PIN_CLKOP : string;
|
|
||||||
attribute FREQUENCY_PIN_CLKI : string;
|
|
||||||
attribute ICP_CURRENT : string;
|
|
||||||
attribute LPF_RESISTOR : string;
|
|
||||||
attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000";
|
|
||||||
attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
|
|
||||||
attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000";
|
|
||||||
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000";
|
|
||||||
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
|
|
||||||
attribute ICP_CURRENT of PLLInst_0 : label is "5";
|
|
||||||
attribute LPF_RESISTOR of PLLInst_0 : label is "16";
|
|
||||||
attribute syn_keep : boolean;
|
|
||||||
attribute NGD_DRC_MASK : integer;
|
|
||||||
attribute NGD_DRC_MASK of rtl : architecture is 1;
|
|
||||||
|
|
||||||
begin
|
|
||||||
-- component instantiation statements
|
|
||||||
scuba_vhi_inst: VHI
|
|
||||||
port map (Z=>scuba_vhi);
|
|
||||||
|
|
||||||
scuba_vlo_inst: VLO
|
|
||||||
port map (Z=>scuba_vlo);
|
|
||||||
|
|
||||||
PLLInst_0: EHXPLLL
|
|
||||||
generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
|
|
||||||
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
|
|
||||||
CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0,
|
|
||||||
CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7,
|
|
||||||
CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0,
|
|
||||||
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
|
|
||||||
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
|
|
||||||
OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
|
|
||||||
OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
|
|
||||||
OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
|
|
||||||
OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60,
|
|
||||||
CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3,
|
|
||||||
CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
|
|
||||||
port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
|
|
||||||
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
|
|
||||||
PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
|
|
||||||
STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
|
|
||||||
ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M,
|
|
||||||
ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
|
|
||||||
CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked,
|
|
||||||
INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
|
|
||||||
|
|
||||||
clk10MHz <= CLKOS3_t;
|
|
||||||
clk50MHz <= CLKOS2_t;
|
|
||||||
clk75MHz <= CLKOS_t;
|
|
||||||
clk60MHz <= CLKOP_t;
|
|
||||||
end rtl;
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
--
|
--
|
||||||
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion
|
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS2.masterVersion
|
||||||
--
|
--
|
||||||
-- Created:
|
-- Created:
|
||||||
-- by - axel.amand.UNKNOWN (WE7860)
|
-- by - axel.amand.UNKNOWN (WE7860)
|
||||||
-- at - 17:45:49 01.05.2023
|
-- at - 14:46:55 28.04.2023
|
||||||
--
|
--
|
||||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
--
|
--
|
||||||
@ -1451,10 +1357,9 @@ LIBRARY ieee;
|
|||||||
USE ieee.numeric_std.all;
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
LIBRARY Board;
|
LIBRARY Board;
|
||||||
LIBRARY Lattice;
|
|
||||||
LIBRARY Lissajous;
|
LIBRARY Lissajous;
|
||||||
|
|
||||||
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS2 IS
|
||||||
|
|
||||||
-- Architecture declarations
|
-- Architecture declarations
|
||||||
constant signalBitNb: positive := 16;
|
constant signalBitNb: positive := 16;
|
||||||
@ -1463,12 +1368,10 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
|||||||
constant stepY: positive := 4;
|
constant stepY: positive := 4;
|
||||||
|
|
||||||
-- Internal signal declarations
|
-- Internal signal declarations
|
||||||
SIGNAL clkSys : std_ulogic;
|
SIGNAL logic1 : std_uLogic;
|
||||||
SIGNAL logic0 : std_ulogic;
|
SIGNAL reset : std_ulogic;
|
||||||
SIGNAL logic1 : std_uLogic;
|
SIGNAL resetSnch_N : std_ulogic;
|
||||||
SIGNAL reset : std_ulogic;
|
SIGNAL resetSynch : std_ulogic;
|
||||||
SIGNAL resetSynch : std_ulogic;
|
|
||||||
SIGNAL resetSynch_N : std_ulogic;
|
|
||||||
|
|
||||||
|
|
||||||
-- Component Declarations
|
-- Component Declarations
|
||||||
@ -1486,19 +1389,6 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
|||||||
out1 : OUT std_uLogic
|
out1 : OUT std_uLogic
|
||||||
);
|
);
|
||||||
END COMPONENT;
|
END COMPONENT;
|
||||||
COMPONENT pll
|
|
||||||
PORT (
|
|
||||||
clkIn100M : IN std_ulogic ;
|
|
||||||
en75M : IN std_ulogic ;
|
|
||||||
en50M : IN std_ulogic ;
|
|
||||||
en10M : IN std_ulogic ;
|
|
||||||
clk60MHz : OUT std_ulogic ;
|
|
||||||
clk75MHz : OUT std_ulogic ;
|
|
||||||
clk50MHz : OUT std_ulogic ;
|
|
||||||
clk10MHz : OUT std_ulogic ;
|
|
||||||
pllLocked : OUT std_ulogic
|
|
||||||
);
|
|
||||||
END COMPONENT;
|
|
||||||
COMPONENT lissajousGenerator
|
COMPONENT lissajousGenerator
|
||||||
GENERIC (
|
GENERIC (
|
||||||
signalBitNb : positive := 16;
|
signalBitNb : positive := 16;
|
||||||
@ -1520,18 +1410,14 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
|||||||
FOR ALL : DFF USE ENTITY Board.DFF;
|
FOR ALL : DFF USE ENTITY Board.DFF;
|
||||||
FOR ALL : inverterIn USE ENTITY Board.inverterIn;
|
FOR ALL : inverterIn USE ENTITY Board.inverterIn;
|
||||||
FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
|
FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
|
||||||
FOR ALL : pll USE ENTITY Lattice.pll;
|
|
||||||
-- pragma synthesis_on
|
-- pragma synthesis_on
|
||||||
|
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
-- Architecture concurrent statements
|
-- Architecture concurrent statements
|
||||||
-- HDL Embedded Text Block 5 eb5
|
-- HDL Embedded Text Block 4 eb4
|
||||||
logic1 <= '1';
|
logic1 <= '1';
|
||||||
|
|
||||||
-- HDL Embedded Text Block 6 eb6
|
|
||||||
logic0 <= '0';
|
|
||||||
|
|
||||||
|
|
||||||
-- Instance port mappings.
|
-- Instance port mappings.
|
||||||
I_dff : DFF
|
I_dff : DFF
|
||||||
@ -1539,7 +1425,7 @@ BEGIN
|
|||||||
CLK => clock,
|
CLK => clock,
|
||||||
CLR => reset,
|
CLR => reset,
|
||||||
D => logic1,
|
D => logic1,
|
||||||
Q => resetSynch_N
|
Q => resetSnch_N
|
||||||
);
|
);
|
||||||
I_inv1 : inverterIn
|
I_inv1 : inverterIn
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
@ -1548,21 +1434,9 @@ BEGIN
|
|||||||
);
|
);
|
||||||
I_inv2 : inverterIn
|
I_inv2 : inverterIn
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
in1 => resetSynch_N,
|
in1 => resetSnch_N,
|
||||||
out1 => resetSynch
|
out1 => resetSynch
|
||||||
);
|
);
|
||||||
U_pll : pll
|
|
||||||
PORT MAP (
|
|
||||||
clkIn100M => clock,
|
|
||||||
en75M => logic0,
|
|
||||||
en50M => logic0,
|
|
||||||
en10M => logic0,
|
|
||||||
clk60MHz => clkSys,
|
|
||||||
clk75MHz => OPEN,
|
|
||||||
clk50MHz => OPEN,
|
|
||||||
clk10MHz => OPEN,
|
|
||||||
pllLocked => OPEN
|
|
||||||
);
|
|
||||||
I_main : lissajousGenerator
|
I_main : lissajousGenerator
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
signalBitNb => signalBitNb,
|
signalBitNb => signalBitNb,
|
||||||
@ -1571,7 +1445,7 @@ BEGIN
|
|||||||
stepY => stepY
|
stepY => stepY
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
clock => clkSys,
|
clock => clock,
|
||||||
reset => resetSynch,
|
reset => resetSynch,
|
||||||
triggerOut => triggerOut,
|
triggerOut => triggerOut,
|
||||||
xOut => xOut,
|
xOut => xOut,
|
||||||
|
|||||||
@ -1,8 +1,8 @@
|
|||||||
-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol
|
-- VHDL Entity Board.lissajousGenerator_circuit_EBS2.symbol
|
||||||
--
|
--
|
||||||
-- Created:
|
-- Created:
|
||||||
-- by - axel.amand.UNKNOWN (WE7860)
|
-- by - francois.francois (Aphelia)
|
||||||
-- at - 17:45:49 01.05.2023
|
-- at - 13:07:18 02/19/19
|
||||||
--
|
--
|
||||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
--
|
--
|
||||||
@ -10,7 +10,10 @@ LIBRARY ieee;
|
|||||||
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_1164.all;
|
||||||
USE ieee.numeric_std.all;
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
ENTITY lissajousGenerator_circuit_EBS3 IS
|
ENTITY lissajousGenerator_circuit_EBS2 IS
|
||||||
|
GENERIC(
|
||||||
|
bitNb : positive := 16
|
||||||
|
);
|
||||||
PORT(
|
PORT(
|
||||||
clock : IN std_ulogic;
|
clock : IN std_ulogic;
|
||||||
reset_N : IN std_ulogic;
|
reset_N : IN std_ulogic;
|
||||||
@ -21,7 +24,7 @@ ENTITY lissajousGenerator_circuit_EBS3 IS
|
|||||||
|
|
||||||
-- Declarations
|
-- Declarations
|
||||||
|
|
||||||
END lissajousGenerator_circuit_EBS3 ;
|
END lissajousGenerator_circuit_EBS2 ;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@ -1340,109 +1343,12 @@ END struct;
|
|||||||
|
|
||||||
|
|
||||||
|
|
||||||
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
|
|
||||||
-- Module Version: 5.7
|
|
||||||
--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc
|
|
||||||
|
|
||||||
-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks
|
|
||||||
|
|
||||||
library IEEE;
|
|
||||||
use IEEE.std_logic_1164.all;
|
|
||||||
library ECP5U;
|
|
||||||
use ECP5U.components.all;
|
|
||||||
|
|
||||||
ENTITY pll IS
|
|
||||||
PORT(
|
|
||||||
clkIn100M : IN std_ulogic;
|
|
||||||
en75M : IN std_ulogic;
|
|
||||||
en50M : IN std_ulogic;
|
|
||||||
en10M : IN std_ulogic;
|
|
||||||
clk60MHz : OUT std_ulogic;
|
|
||||||
clk75MHz : OUT std_ulogic;
|
|
||||||
clk50MHz : OUT std_ulogic;
|
|
||||||
clk10MHz : OUT std_ulogic;
|
|
||||||
pllLocked : OUT std_ulogic
|
|
||||||
);
|
|
||||||
|
|
||||||
-- Declarations
|
|
||||||
|
|
||||||
END pll ;
|
|
||||||
|
|
||||||
architecture rtl of pll is
|
|
||||||
|
|
||||||
-- internal signal declarations
|
|
||||||
signal REFCLK: std_logic;
|
|
||||||
signal CLKOS3_t: std_logic;
|
|
||||||
signal CLKOS2_t: std_logic;
|
|
||||||
signal CLKOS_t: std_logic;
|
|
||||||
signal CLKOP_t: std_logic;
|
|
||||||
signal scuba_vhi: std_logic;
|
|
||||||
signal scuba_vlo: std_logic;
|
|
||||||
|
|
||||||
attribute FREQUENCY_PIN_CLKOS3 : string;
|
|
||||||
attribute FREQUENCY_PIN_CLKOS2 : string;
|
|
||||||
attribute FREQUENCY_PIN_CLKOS : string;
|
|
||||||
attribute FREQUENCY_PIN_CLKOP : string;
|
|
||||||
attribute FREQUENCY_PIN_CLKI : string;
|
|
||||||
attribute ICP_CURRENT : string;
|
|
||||||
attribute LPF_RESISTOR : string;
|
|
||||||
attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000";
|
|
||||||
attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
|
|
||||||
attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000";
|
|
||||||
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000";
|
|
||||||
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
|
|
||||||
attribute ICP_CURRENT of PLLInst_0 : label is "5";
|
|
||||||
attribute LPF_RESISTOR of PLLInst_0 : label is "16";
|
|
||||||
attribute syn_keep : boolean;
|
|
||||||
attribute NGD_DRC_MASK : integer;
|
|
||||||
attribute NGD_DRC_MASK of rtl : architecture is 1;
|
|
||||||
|
|
||||||
begin
|
|
||||||
-- component instantiation statements
|
|
||||||
scuba_vhi_inst: VHI
|
|
||||||
port map (Z=>scuba_vhi);
|
|
||||||
|
|
||||||
scuba_vlo_inst: VLO
|
|
||||||
port map (Z=>scuba_vlo);
|
|
||||||
|
|
||||||
PLLInst_0: EHXPLLL
|
|
||||||
generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
|
|
||||||
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
|
|
||||||
CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0,
|
|
||||||
CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7,
|
|
||||||
CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0,
|
|
||||||
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
|
|
||||||
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
|
|
||||||
OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
|
|
||||||
OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
|
|
||||||
OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
|
|
||||||
OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60,
|
|
||||||
CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3,
|
|
||||||
CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
|
|
||||||
port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
|
|
||||||
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
|
|
||||||
PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
|
|
||||||
STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
|
|
||||||
ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M,
|
|
||||||
ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
|
|
||||||
CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked,
|
|
||||||
INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
|
|
||||||
|
|
||||||
clk10MHz <= CLKOS3_t;
|
|
||||||
clk50MHz <= CLKOS2_t;
|
|
||||||
clk75MHz <= CLKOS_t;
|
|
||||||
clk60MHz <= CLKOP_t;
|
|
||||||
end rtl;
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
--
|
--
|
||||||
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion
|
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS2.masterVersion
|
||||||
--
|
--
|
||||||
-- Created:
|
-- Created:
|
||||||
-- by - axel.amand.UNKNOWN (WE7860)
|
-- by - axel.amand.UNKNOWN (WE7860)
|
||||||
-- at - 17:45:49 01.05.2023
|
-- at - 14:46:55 28.04.2023
|
||||||
--
|
--
|
||||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
--
|
--
|
||||||
@ -1451,10 +1357,9 @@ LIBRARY ieee;
|
|||||||
USE ieee.numeric_std.all;
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
-- LIBRARY Board;
|
-- LIBRARY Board;
|
||||||
-- LIBRARY Lattice;
|
|
||||||
-- LIBRARY Lissajous;
|
-- LIBRARY Lissajous;
|
||||||
|
|
||||||
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS2 IS
|
||||||
|
|
||||||
-- Architecture declarations
|
-- Architecture declarations
|
||||||
constant signalBitNb: positive := 16;
|
constant signalBitNb: positive := 16;
|
||||||
@ -1463,12 +1368,10 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
|||||||
constant stepY: positive := 4;
|
constant stepY: positive := 4;
|
||||||
|
|
||||||
-- Internal signal declarations
|
-- Internal signal declarations
|
||||||
SIGNAL clkSys : std_ulogic;
|
SIGNAL logic1 : std_uLogic;
|
||||||
SIGNAL logic0 : std_ulogic;
|
SIGNAL reset : std_ulogic;
|
||||||
SIGNAL logic1 : std_uLogic;
|
SIGNAL resetSnch_N : std_ulogic;
|
||||||
SIGNAL reset : std_ulogic;
|
SIGNAL resetSynch : std_ulogic;
|
||||||
SIGNAL resetSynch : std_ulogic;
|
|
||||||
SIGNAL resetSynch_N : std_ulogic;
|
|
||||||
|
|
||||||
|
|
||||||
-- Component Declarations
|
-- Component Declarations
|
||||||
@ -1486,19 +1389,6 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
|||||||
out1 : OUT std_uLogic
|
out1 : OUT std_uLogic
|
||||||
);
|
);
|
||||||
END COMPONENT;
|
END COMPONENT;
|
||||||
COMPONENT pll
|
|
||||||
PORT (
|
|
||||||
clkIn100M : IN std_ulogic ;
|
|
||||||
en75M : IN std_ulogic ;
|
|
||||||
en50M : IN std_ulogic ;
|
|
||||||
en10M : IN std_ulogic ;
|
|
||||||
clk60MHz : OUT std_ulogic ;
|
|
||||||
clk75MHz : OUT std_ulogic ;
|
|
||||||
clk50MHz : OUT std_ulogic ;
|
|
||||||
clk10MHz : OUT std_ulogic ;
|
|
||||||
pllLocked : OUT std_ulogic
|
|
||||||
);
|
|
||||||
END COMPONENT;
|
|
||||||
COMPONENT lissajousGenerator
|
COMPONENT lissajousGenerator
|
||||||
GENERIC (
|
GENERIC (
|
||||||
signalBitNb : positive := 16;
|
signalBitNb : positive := 16;
|
||||||
@ -1520,18 +1410,14 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
|||||||
-- FOR ALL : DFF USE ENTITY Board.DFF;
|
-- FOR ALL : DFF USE ENTITY Board.DFF;
|
||||||
-- FOR ALL : inverterIn USE ENTITY Board.inverterIn;
|
-- FOR ALL : inverterIn USE ENTITY Board.inverterIn;
|
||||||
-- FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
|
-- FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
|
||||||
-- FOR ALL : pll USE ENTITY Lattice.pll;
|
|
||||||
-- pragma synthesis_on
|
-- pragma synthesis_on
|
||||||
|
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
-- Architecture concurrent statements
|
-- Architecture concurrent statements
|
||||||
-- HDL Embedded Text Block 5 eb5
|
-- HDL Embedded Text Block 4 eb4
|
||||||
logic1 <= '1';
|
logic1 <= '1';
|
||||||
|
|
||||||
-- HDL Embedded Text Block 6 eb6
|
|
||||||
logic0 <= '0';
|
|
||||||
|
|
||||||
|
|
||||||
-- Instance port mappings.
|
-- Instance port mappings.
|
||||||
I_dff : DFF
|
I_dff : DFF
|
||||||
@ -1539,7 +1425,7 @@ BEGIN
|
|||||||
CLK => clock,
|
CLK => clock,
|
||||||
CLR => reset,
|
CLR => reset,
|
||||||
D => logic1,
|
D => logic1,
|
||||||
Q => resetSynch_N
|
Q => resetSnch_N
|
||||||
);
|
);
|
||||||
I_inv1 : inverterIn
|
I_inv1 : inverterIn
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
@ -1548,21 +1434,9 @@ BEGIN
|
|||||||
);
|
);
|
||||||
I_inv2 : inverterIn
|
I_inv2 : inverterIn
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
in1 => resetSynch_N,
|
in1 => resetSnch_N,
|
||||||
out1 => resetSynch
|
out1 => resetSynch
|
||||||
);
|
);
|
||||||
U_pll : pll
|
|
||||||
PORT MAP (
|
|
||||||
clkIn100M => clock,
|
|
||||||
en75M => logic0,
|
|
||||||
en50M => logic0,
|
|
||||||
en10M => logic0,
|
|
||||||
clk60MHz => clkSys,
|
|
||||||
clk75MHz => OPEN,
|
|
||||||
clk50MHz => OPEN,
|
|
||||||
clk10MHz => OPEN,
|
|
||||||
pllLocked => OPEN
|
|
||||||
);
|
|
||||||
I_main : lissajousGenerator
|
I_main : lissajousGenerator
|
||||||
GENERIC MAP (
|
GENERIC MAP (
|
||||||
signalBitNb => signalBitNb,
|
signalBitNb => signalBitNb,
|
||||||
@ -1571,7 +1445,7 @@ BEGIN
|
|||||||
stepY => stepY
|
stepY => stepY
|
||||||
)
|
)
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
clock => clkSys,
|
clock => clock,
|
||||||
reset => resetSynch,
|
reset => resetSynch,
|
||||||
triggerOut => triggerOut,
|
triggerOut => triggerOut,
|
||||||
xOut => xOut,
|
xOut => xOut,
|
||||||
|
|||||||
23
zz-solutions/04-Lissajous/Board/hdl/dff_entity.vhg
Normal file
23
zz-solutions/04-Lissajous/Board/hdl/dff_entity.vhg
Normal file
@ -0,0 +1,23 @@
|
|||||||
|
-- VHDL Entity Board.DFF.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - francois.francois (Aphelia)
|
||||||
|
-- at - 13:07:05 02/19/19
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
|
||||||
|
ENTITY DFF IS
|
||||||
|
PORT(
|
||||||
|
CLK : IN std_uLogic;
|
||||||
|
CLR : IN std_uLogic;
|
||||||
|
D : IN std_uLogic;
|
||||||
|
Q : OUT std_uLogic
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END DFF ;
|
||||||
|
|
||||||
21
zz-solutions/04-Lissajous/Board/hdl/inverterin_entity.vhg
Normal file
21
zz-solutions/04-Lissajous/Board/hdl/inverterin_entity.vhg
Normal file
@ -0,0 +1,21 @@
|
|||||||
|
-- VHDL Entity Board.inverterIn.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - francois.francois (Aphelia)
|
||||||
|
-- at - 13:07:14 02/19/19
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
|
||||||
|
ENTITY inverterIn IS
|
||||||
|
PORT(
|
||||||
|
in1 : IN std_uLogic;
|
||||||
|
out1 : OUT std_uLogic
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END inverterIn ;
|
||||||
|
|
||||||
@ -0,0 +1,28 @@
|
|||||||
|
-- VHDL Entity Board.lissajousGenerator_circuit_EBS2.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - francois.francois (Aphelia)
|
||||||
|
-- at - 13:07:18 02/19/19
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
ENTITY lissajousGenerator_circuit_EBS2 IS
|
||||||
|
GENERIC(
|
||||||
|
bitNb : positive := 16
|
||||||
|
);
|
||||||
|
PORT(
|
||||||
|
clock : IN std_ulogic;
|
||||||
|
reset_N : IN std_ulogic;
|
||||||
|
triggerOut : OUT std_ulogic;
|
||||||
|
xOut : OUT std_ulogic;
|
||||||
|
yOut : OUT std_ulogic
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END lissajousGenerator_circuit_EBS2 ;
|
||||||
|
|
||||||
@ -0,0 +1,110 @@
|
|||||||
|
--
|
||||||
|
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS2.masterVersion
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - axel.amand.UNKNOWN (WE7860)
|
||||||
|
-- at - 14:46:55 28.04.2023
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
LIBRARY Board;
|
||||||
|
LIBRARY Lissajous;
|
||||||
|
|
||||||
|
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS2 IS
|
||||||
|
|
||||||
|
-- Architecture declarations
|
||||||
|
constant signalBitNb: positive := 16;
|
||||||
|
constant phaseBitNb: positive := 17;
|
||||||
|
constant stepX: positive := 3;
|
||||||
|
constant stepY: positive := 4;
|
||||||
|
|
||||||
|
-- Internal signal declarations
|
||||||
|
SIGNAL logic1 : std_uLogic;
|
||||||
|
SIGNAL reset : std_ulogic;
|
||||||
|
SIGNAL resetSnch_N : std_ulogic;
|
||||||
|
SIGNAL resetSynch : std_ulogic;
|
||||||
|
|
||||||
|
|
||||||
|
-- Component Declarations
|
||||||
|
COMPONENT DFF
|
||||||
|
PORT (
|
||||||
|
CLK : IN std_uLogic ;
|
||||||
|
CLR : IN std_uLogic ;
|
||||||
|
D : IN std_uLogic ;
|
||||||
|
Q : OUT std_uLogic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
COMPONENT inverterIn
|
||||||
|
PORT (
|
||||||
|
in1 : IN std_uLogic ;
|
||||||
|
out1 : OUT std_uLogic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
COMPONENT lissajousGenerator
|
||||||
|
GENERIC (
|
||||||
|
signalBitNb : positive := 16;
|
||||||
|
phaseBitNb : positive := 16;
|
||||||
|
stepX : positive := 1;
|
||||||
|
stepY : positive := 1
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
clock : IN std_ulogic ;
|
||||||
|
reset : IN std_ulogic ;
|
||||||
|
triggerOut : OUT std_ulogic ;
|
||||||
|
xOut : OUT std_ulogic ;
|
||||||
|
yOut : OUT std_ulogic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
-- Optional embedded configurations
|
||||||
|
-- pragma synthesis_off
|
||||||
|
FOR ALL : DFF USE ENTITY Board.DFF;
|
||||||
|
FOR ALL : inverterIn USE ENTITY Board.inverterIn;
|
||||||
|
FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
|
||||||
|
-- pragma synthesis_on
|
||||||
|
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
-- Architecture concurrent statements
|
||||||
|
-- HDL Embedded Text Block 4 eb4
|
||||||
|
logic1 <= '1';
|
||||||
|
|
||||||
|
|
||||||
|
-- Instance port mappings.
|
||||||
|
I_dff : DFF
|
||||||
|
PORT MAP (
|
||||||
|
CLK => clock,
|
||||||
|
CLR => reset,
|
||||||
|
D => logic1,
|
||||||
|
Q => resetSnch_N
|
||||||
|
);
|
||||||
|
I_inv1 : inverterIn
|
||||||
|
PORT MAP (
|
||||||
|
in1 => reset_N,
|
||||||
|
out1 => reset
|
||||||
|
);
|
||||||
|
I_inv2 : inverterIn
|
||||||
|
PORT MAP (
|
||||||
|
in1 => resetSnch_N,
|
||||||
|
out1 => resetSynch
|
||||||
|
);
|
||||||
|
I_main : lissajousGenerator
|
||||||
|
GENERIC MAP (
|
||||||
|
signalBitNb => signalBitNb,
|
||||||
|
phaseBitNb => phaseBitNb,
|
||||||
|
stepX => stepX,
|
||||||
|
stepY => stepY
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
clock => clock,
|
||||||
|
reset => resetSynch,
|
||||||
|
triggerOut => triggerOut,
|
||||||
|
xOut => xOut,
|
||||||
|
yOut => yOut
|
||||||
|
);
|
||||||
|
|
||||||
|
END masterVersion;
|
||||||
@ -0,0 +1,25 @@
|
|||||||
|
-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - axel.amand.UNKNOWN (WE7860)
|
||||||
|
-- at - 17:45:49 01.05.2023
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
ENTITY lissajousGenerator_circuit_EBS3 IS
|
||||||
|
PORT(
|
||||||
|
clock : IN std_ulogic;
|
||||||
|
reset_N : IN std_ulogic;
|
||||||
|
triggerOut : OUT std_ulogic;
|
||||||
|
xOut : OUT std_ulogic;
|
||||||
|
yOut : OUT std_ulogic
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END lissajousGenerator_circuit_EBS3 ;
|
||||||
|
|
||||||
@ -0,0 +1,142 @@
|
|||||||
|
--
|
||||||
|
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - axel.amand.UNKNOWN (WE7860)
|
||||||
|
-- at - 17:45:49 01.05.2023
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
LIBRARY Board;
|
||||||
|
LIBRARY Lattice;
|
||||||
|
LIBRARY Lissajous;
|
||||||
|
|
||||||
|
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
||||||
|
|
||||||
|
-- Architecture declarations
|
||||||
|
constant signalBitNb: positive := 16;
|
||||||
|
constant phaseBitNb: positive := 17;
|
||||||
|
constant stepX: positive := 3;
|
||||||
|
constant stepY: positive := 4;
|
||||||
|
|
||||||
|
-- Internal signal declarations
|
||||||
|
SIGNAL clkSys : std_ulogic;
|
||||||
|
SIGNAL logic0 : std_ulogic;
|
||||||
|
SIGNAL logic1 : std_uLogic;
|
||||||
|
SIGNAL reset : std_ulogic;
|
||||||
|
SIGNAL resetSynch : std_ulogic;
|
||||||
|
SIGNAL resetSynch_N : std_ulogic;
|
||||||
|
|
||||||
|
|
||||||
|
-- Component Declarations
|
||||||
|
COMPONENT DFF
|
||||||
|
PORT (
|
||||||
|
CLK : IN std_uLogic ;
|
||||||
|
CLR : IN std_uLogic ;
|
||||||
|
D : IN std_uLogic ;
|
||||||
|
Q : OUT std_uLogic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
COMPONENT inverterIn
|
||||||
|
PORT (
|
||||||
|
in1 : IN std_uLogic ;
|
||||||
|
out1 : OUT std_uLogic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
COMPONENT pll
|
||||||
|
PORT (
|
||||||
|
clkIn100M : IN std_ulogic;
|
||||||
|
en10M : IN std_ulogic;
|
||||||
|
en50M : IN std_ulogic;
|
||||||
|
en75M : IN std_ulogic;
|
||||||
|
clk10MHz : OUT std_ulogic;
|
||||||
|
clk50MHz : OUT std_ulogic;
|
||||||
|
clk60MHz : OUT std_ulogic;
|
||||||
|
clk75MHz : OUT std_ulogic;
|
||||||
|
pllLocked : OUT std_ulogic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
COMPONENT lissajousGenerator
|
||||||
|
GENERIC (
|
||||||
|
signalBitNb : positive := 16;
|
||||||
|
phaseBitNb : positive := 16;
|
||||||
|
stepX : positive := 1;
|
||||||
|
stepY : positive := 1
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
clock : IN std_ulogic ;
|
||||||
|
reset : IN std_ulogic ;
|
||||||
|
triggerOut : OUT std_ulogic ;
|
||||||
|
xOut : OUT std_ulogic ;
|
||||||
|
yOut : OUT std_ulogic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
-- Optional embedded configurations
|
||||||
|
-- pragma synthesis_off
|
||||||
|
FOR ALL : DFF USE ENTITY Board.DFF;
|
||||||
|
FOR ALL : inverterIn USE ENTITY Board.inverterIn;
|
||||||
|
FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
|
||||||
|
FOR ALL : pll USE ENTITY Lattice.pll;
|
||||||
|
-- pragma synthesis_on
|
||||||
|
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
-- Architecture concurrent statements
|
||||||
|
-- HDL Embedded Text Block 5 eb5
|
||||||
|
logic1 <= '1';
|
||||||
|
|
||||||
|
-- HDL Embedded Text Block 6 eb6
|
||||||
|
logic0 <= '0';
|
||||||
|
|
||||||
|
|
||||||
|
-- Instance port mappings.
|
||||||
|
I_dff : DFF
|
||||||
|
PORT MAP (
|
||||||
|
CLK => clock,
|
||||||
|
CLR => reset,
|
||||||
|
D => logic1,
|
||||||
|
Q => resetSynch_N
|
||||||
|
);
|
||||||
|
I_inv1 : inverterIn
|
||||||
|
PORT MAP (
|
||||||
|
in1 => reset_N,
|
||||||
|
out1 => reset
|
||||||
|
);
|
||||||
|
I_inv2 : inverterIn
|
||||||
|
PORT MAP (
|
||||||
|
in1 => resetSynch_N,
|
||||||
|
out1 => resetSynch
|
||||||
|
);
|
||||||
|
U_pll : pll
|
||||||
|
PORT MAP (
|
||||||
|
clkIn100M => clock,
|
||||||
|
en75M => logic0,
|
||||||
|
en50M => logic0,
|
||||||
|
en10M => logic0,
|
||||||
|
clk60MHz => clkSys,
|
||||||
|
clk75MHz => OPEN,
|
||||||
|
clk50MHz => OPEN,
|
||||||
|
clk10MHz => OPEN,
|
||||||
|
pllLocked => OPEN
|
||||||
|
);
|
||||||
|
I_main : lissajousGenerator
|
||||||
|
GENERIC MAP (
|
||||||
|
signalBitNb => signalBitNb,
|
||||||
|
phaseBitNb => phaseBitNb,
|
||||||
|
stepX => stepX,
|
||||||
|
stepY => stepY
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
clock => clkSys,
|
||||||
|
reset => resetSynch,
|
||||||
|
triggerOut => triggerOut,
|
||||||
|
xOut => xOut,
|
||||||
|
yOut => yOut
|
||||||
|
);
|
||||||
|
|
||||||
|
END masterVersion;
|
||||||
BIN
zz-solutions/04-Lissajous/Board/hds/.cache.dat
Normal file
BIN
zz-solutions/04-Lissajous/Board/hds/.cache.dat
Normal file
Binary file not shown.
@ -0,0 +1 @@
|
|||||||
|
DIALECT atom VHDL_2008
|
||||||
@ -0,0 +1 @@
|
|||||||
|
DIALECT atom VHDL_2008
|
||||||
24
zz-solutions/04-Lissajous/Board/hds/.xrf/dff_entity.xrf
Normal file
24
zz-solutions/04-Lissajous/Board/hds/.xrf/dff_entity.xrf
Normal file
@ -0,0 +1,24 @@
|
|||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 98,0 8 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 13 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 63,0 14 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 51,0 15 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 69,0 16 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 19 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 20 0
|
||||||
@ -0,0 +1,18 @@
|
|||||||
|
DESIGN inverter@in
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN inverter@in
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 41,0 8 0
|
||||||
|
DESIGN inverter@in
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 16,0 13 0
|
||||||
|
DESIGN inverter@in
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 22,0 14 0
|
||||||
|
DESIGN inverter@in
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 31,0 17 0
|
||||||
|
DESIGN inverter@in
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 31,0 18 0
|
||||||
@ -0,0 +1,30 @@
|
|||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 50,0 8 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 13,0 13 1
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 17 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 83,0 18 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 88,0 19 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 93,0 20 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 98,0 21 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 24 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 25 0
|
||||||
@ -0,0 +1,165 @@
|
|||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 84,0 9 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 12
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 0,0 16 2
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 1,0 19 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 19
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 895,0 25 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 49,0 26 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 893,0 27 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 897,0 28 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 29
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 30
|
||||||
|
LIBRARY Board
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW sim
|
||||||
|
GRAPHIC 1071,0 32 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 34 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 63,0 35 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 51,0 36 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 69,0 37 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 1817,0 40 0
|
||||||
|
DESIGN inverter@in
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 16,0 42 0
|
||||||
|
DESIGN inverter@in
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 22,0 43 0
|
||||||
|
LIBRARY Lissajous
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct
|
||||||
|
GRAPHIC 2310,0 46 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 14,0 47 1
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 54 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 428,0 55 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 88,0 56 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 93,0 57 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 98,0 58 0
|
||||||
|
LIBRARY Board
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 61
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 1071,0 64 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 1817,0 65 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 2310,0 66 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 69
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 818,0 72 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 74
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 75
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 1071,0 77 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 873,0 79 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 879,0 80 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 887,0 81 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 883,0 82 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 1817,0 84 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 43,0 86 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 879,0 87 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 1806,0 89 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 883,0 91 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 245,0 92 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 2310,0 94 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 2317,0 95 1
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 15,0 102 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 245,0 103 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 435,0 104 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 575,0 105 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 29,0 106 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s2
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 109
|
||||||
@ -0,0 +1,27 @@
|
|||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 50,0 8 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 118,0 14 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 128,0 15 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 123,0 16 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 133,0 17 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 138,0 18 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 21 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 22 0
|
||||||
@ -0,0 +1,205 @@
|
|||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 41,0 9 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 12
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 0,0 17 2
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 1,0 20 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 20
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 380,0 26 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 411,0 27 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 370,0 28 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 360,0 29 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 368,0 30 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 464,0 31 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 32
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 33
|
||||||
|
LIBRARY Board
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW sim
|
||||||
|
GRAPHIC 219,0 35 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 37 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 63,0 38 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 51,0 39 0
|
||||||
|
DESIGN @d@f@f
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 69,0 40 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 199,0 43 0
|
||||||
|
DESIGN inverter@in
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 16,0 45 0
|
||||||
|
DESIGN inverter@in
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 22,0 46 0
|
||||||
|
LIBRARY Board
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version
|
||||||
|
GRAPHIC 168,0 49 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 60
|
||||||
|
LIBRARY Lissajous
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct
|
||||||
|
GRAPHIC 265,0 62 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 14,0 63 1
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 70 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 428,0 71 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 88,0 72 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 93,0 73 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 98,0 74 0
|
||||||
|
LIBRARY Board
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 77
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 219,0 80 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 199,0 81 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 265,0 82 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 168,0 83 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 86
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 190,0 89 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 91
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 382,0 92 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 94
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 95
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 219,0 97 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 328,0 99 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 320,0 100 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 338,0 101 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 334,0 102 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 199,0 104 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 348,0 106 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 320,0 107 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 245,0 109 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 334,0 111 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 352,0 112 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 168,0 114 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 312,0 116 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 393,0 117 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 405,0 118 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 399,0 119 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 376,0 120 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 265,0 126 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 272,0 127 1
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 376,0 134 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 352,0 135 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 324,0 136 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 344,0 137 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
GRAPHIC 316,0 138 0
|
||||||
|
DESIGN lissajous@generator_circuit_@e@b@s3
|
||||||
|
VIEW master@version.bd
|
||||||
|
NO_GRAPHIC 141
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
-- VHDL Entity Lissajous.lissajousGenerator.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - francois.francois (Aphelia)
|
||||||
|
-- at - 13:07:53 02/19/19
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
ENTITY lissajousGenerator IS
|
||||||
|
GENERIC(
|
||||||
|
signalBitNb : positive := 16;
|
||||||
|
phaseBitNb : positive := 16;
|
||||||
|
stepX : positive := 1;
|
||||||
|
stepY : positive := 1
|
||||||
|
);
|
||||||
|
PORT(
|
||||||
|
clock : IN std_ulogic;
|
||||||
|
reset : IN std_ulogic;
|
||||||
|
triggerOut : OUT std_ulogic;
|
||||||
|
xOut : OUT std_ulogic;
|
||||||
|
yOut : OUT std_ulogic
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END lissajousGenerator ;
|
||||||
|
|
||||||
@ -0,0 +1,126 @@
|
|||||||
|
--
|
||||||
|
-- VHDL Architecture Lissajous.lissajousGenerator.struct
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - axel.amand.UNKNOWN (WE7860)
|
||||||
|
-- at - 14:47:09 28.04.2023
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.all;
|
||||||
|
|
||||||
|
LIBRARY DigitalToAnalogConverter;
|
||||||
|
LIBRARY SplineInterpolator;
|
||||||
|
|
||||||
|
ARCHITECTURE struct OF lissajousGenerator IS
|
||||||
|
|
||||||
|
-- Architecture declarations
|
||||||
|
|
||||||
|
-- Internal signal declarations
|
||||||
|
SIGNAL sineX : unsigned(signalBitNb-1 DOWNTO 0);
|
||||||
|
SIGNAL sineY : unsigned(signalBitNb-1 DOWNTO 0);
|
||||||
|
SIGNAL squareY : unsigned(signalBitNb-1 DOWNTO 0);
|
||||||
|
SIGNAL stepXUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
|
||||||
|
SIGNAL stepYUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
|
||||||
|
|
||||||
|
|
||||||
|
-- Component Declarations
|
||||||
|
COMPONENT DAC
|
||||||
|
GENERIC (
|
||||||
|
signalBitNb : positive := 16
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
serialOut : OUT std_ulogic ;
|
||||||
|
parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
clock : IN std_ulogic ;
|
||||||
|
reset : IN std_ulogic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
COMPONENT sineGen
|
||||||
|
GENERIC (
|
||||||
|
signalBitNb : positive := 16;
|
||||||
|
phaseBitNb : positive := 10
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
clock : IN std_ulogic ;
|
||||||
|
reset : IN std_ulogic ;
|
||||||
|
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
|
||||||
|
sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
-- Optional embedded configurations
|
||||||
|
-- pragma synthesis_off
|
||||||
|
FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC;
|
||||||
|
FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen;
|
||||||
|
-- pragma synthesis_on
|
||||||
|
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
-- Architecture concurrent statements
|
||||||
|
-- HDL Embedded Text Block 1 eb1
|
||||||
|
triggerOut <= squareY(squareY'high);
|
||||||
|
|
||||||
|
-- HDL Embedded Text Block 2 eb2
|
||||||
|
stepXUnsigned <= to_unsigned(stepX, stepXUnsigned'length);
|
||||||
|
|
||||||
|
-- HDL Embedded Text Block 3 eb3
|
||||||
|
stepYUnsigned <= to_unsigned(stepY, stepYUnsigned'length);
|
||||||
|
|
||||||
|
|
||||||
|
-- Instance port mappings.
|
||||||
|
I_dacX : DAC
|
||||||
|
GENERIC MAP (
|
||||||
|
signalBitNb => signalBitNb
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
serialOut => xOut,
|
||||||
|
parallelIn => sineX,
|
||||||
|
clock => clock,
|
||||||
|
reset => reset
|
||||||
|
);
|
||||||
|
I_dacY : DAC
|
||||||
|
GENERIC MAP (
|
||||||
|
signalBitNb => signalBitNb
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
serialOut => yOut,
|
||||||
|
parallelIn => sineY,
|
||||||
|
clock => clock,
|
||||||
|
reset => reset
|
||||||
|
);
|
||||||
|
I_sinX : sineGen
|
||||||
|
GENERIC MAP (
|
||||||
|
signalBitNb => signalBitNb,
|
||||||
|
phaseBitNb => phaseBitNb
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
clock => clock,
|
||||||
|
reset => reset,
|
||||||
|
step => stepXUnsigned,
|
||||||
|
sawtooth => OPEN,
|
||||||
|
sine => sineX,
|
||||||
|
square => OPEN,
|
||||||
|
triangle => OPEN
|
||||||
|
);
|
||||||
|
I_sinY : sineGen
|
||||||
|
GENERIC MAP (
|
||||||
|
signalBitNb => signalBitNb,
|
||||||
|
phaseBitNb => phaseBitNb
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
clock => clock,
|
||||||
|
reset => reset,
|
||||||
|
step => stepYUnsigned,
|
||||||
|
sawtooth => OPEN,
|
||||||
|
sine => sineY,
|
||||||
|
square => squareY,
|
||||||
|
triangle => OPEN
|
||||||
|
);
|
||||||
|
|
||||||
|
END struct;
|
||||||
BIN
zz-solutions/04-Lissajous/Lissajous/hds/.cache.dat
Normal file
BIN
zz-solutions/04-Lissajous/Lissajous/hds/.cache.dat
Normal file
Binary file not shown.
@ -0,0 +1,30 @@
|
|||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 50,0 8 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 13,0 13 1
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 20 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 428,0 21 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 88,0 22 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 93,0 23 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 98,0 24 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 27 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 28 0
|
||||||
@ -0,0 +1,192 @@
|
|||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 84,0 9 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 12
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 0,0 16 2
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 617,0 21 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1631,0 22 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1652,0 23 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2512,0 24 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2510,0 25 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 26
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 27
|
||||||
|
LIBRARY DigitalToAnalogConverter
|
||||||
|
DESIGN @d@a@c
|
||||||
|
VIEW master@version
|
||||||
|
GRAPHIC 2187,0 29 0
|
||||||
|
DESIGN @d@a@c
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 14,0 30 1
|
||||||
|
DESIGN @d@a@c
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 67,0 34 0
|
||||||
|
DESIGN @d@a@c
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 35 0
|
||||||
|
DESIGN @d@a@c
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 36 0
|
||||||
|
DESIGN @d@a@c
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 76,0 37 0
|
||||||
|
LIBRARY SplineInterpolator
|
||||||
|
DESIGN sine@gen
|
||||||
|
VIEW struct
|
||||||
|
GRAPHIC 2090,0 40 0
|
||||||
|
DESIGN sine@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 14,0 41 1
|
||||||
|
DESIGN sine@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 46 0
|
||||||
|
DESIGN sine@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 88,0 47 0
|
||||||
|
DESIGN sine@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 128,0 48 0
|
||||||
|
DESIGN sine@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 98,0 49 0
|
||||||
|
DESIGN sine@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 103,0 50 0
|
||||||
|
DESIGN sine@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 108,0 51 0
|
||||||
|
DESIGN sine@gen
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 118,0 52 0
|
||||||
|
LIBRARY Lissajous
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 55
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2187,0 58 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2090,0 59 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 62
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 443,0 65 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 67
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1324,0 68 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 70
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1637,0 71 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 73
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 74
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2187,0 76 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2194,0 77 1
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 575,0 81 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 579,0 82 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 583,0 83 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 589,0 84 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2162,0 86 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2169,0 87 1
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 29,0 91 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1613,0 92 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1617,0 93 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1623,0 94 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2090,0 96 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2097,0 97 1
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2349,0 102 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2341,0 103 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1335,0 104 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 579,0 106 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2053,0 110 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2060,0 111 1
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 15,0 116 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 2357,0 117 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1341,0 118 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1613,0 120 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 450,0 121 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 125
|
||||||
@ -0,0 +1,15 @@
|
|||||||
|
-- VHDL Entity Lissajous_test.lissajousGenerator_test.symbol
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - francois.francois (Aphelia)
|
||||||
|
-- at - 13:07:27 02/19/19
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
|
||||||
|
|
||||||
|
ENTITY lissajousGenerator_test IS
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END lissajousGenerator_test ;
|
||||||
|
|
||||||
@ -0,0 +1,152 @@
|
|||||||
|
--
|
||||||
|
-- VHDL Architecture Lissajous_test.lissajousGenerator_test.struct
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - axel.amand.UNKNOWN (WE7860)
|
||||||
|
-- at - 14:48:46 28.04.2023
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
LIBRARY Lissajous;
|
||||||
|
LIBRARY Lissajous_test;
|
||||||
|
LIBRARY WaveformGenerator;
|
||||||
|
|
||||||
|
ARCHITECTURE struct OF lissajousGenerator_test IS
|
||||||
|
|
||||||
|
-- Architecture declarations
|
||||||
|
constant signalBitNb: positive := 16;
|
||||||
|
constant phaseBitNb: positive := 17;
|
||||||
|
constant stepX: positive := 2;
|
||||||
|
constant stepY: positive := 3;
|
||||||
|
constant lowpassShiftBitNb: positive := 8;
|
||||||
|
constant clockFrequency: real := 60.0E6;
|
||||||
|
--constant clockFrequency: real := 66.0E6;
|
||||||
|
|
||||||
|
-- Internal signal declarations
|
||||||
|
SIGNAL clock : std_ulogic;
|
||||||
|
SIGNAL reset : std_ulogic;
|
||||||
|
SIGNAL triggerOut : std_ulogic;
|
||||||
|
SIGNAL xLowapss : unsigned(signalBitNb-1 DOWNTO 0);
|
||||||
|
SIGNAL xParallel : unsigned(signalBitNb-1 DOWNTO 0);
|
||||||
|
SIGNAL xSerial : std_ulogic;
|
||||||
|
SIGNAL yLowpass : unsigned(signalBitNb-1 DOWNTO 0);
|
||||||
|
SIGNAL yParallel : unsigned(signalBitNb-1 DOWNTO 0);
|
||||||
|
SIGNAL ySerial : std_ulogic;
|
||||||
|
|
||||||
|
|
||||||
|
-- Component Declarations
|
||||||
|
COMPONENT lissajousGenerator
|
||||||
|
GENERIC (
|
||||||
|
signalBitNb : positive := 16;
|
||||||
|
phaseBitNb : positive := 16;
|
||||||
|
stepX : positive := 1;
|
||||||
|
stepY : positive := 1
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
clock : IN std_ulogic ;
|
||||||
|
reset : IN std_ulogic ;
|
||||||
|
triggerOut : OUT std_ulogic ;
|
||||||
|
xOut : OUT std_ulogic ;
|
||||||
|
yOut : OUT std_ulogic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
COMPONENT lissajousGenerator_tester
|
||||||
|
GENERIC (
|
||||||
|
signalBitNb : positive := 16;
|
||||||
|
clockFrequency : real := 60.0E6
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
triggerOut : IN std_ulogic ;
|
||||||
|
xLowapss : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
xSerial : IN std_ulogic ;
|
||||||
|
yLowpass : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
ySerial : IN std_ulogic ;
|
||||||
|
clock : OUT std_ulogic ;
|
||||||
|
reset : OUT std_ulogic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
COMPONENT lowpass
|
||||||
|
GENERIC (
|
||||||
|
signalBitNb : positive := 16;
|
||||||
|
shiftBitNb : positive := 12
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
clock : IN std_ulogic ;
|
||||||
|
reset : IN std_ulogic ;
|
||||||
|
lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
-- Optional embedded configurations
|
||||||
|
-- pragma synthesis_off
|
||||||
|
FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
|
||||||
|
FOR ALL : lissajousGenerator_tester USE ENTITY Lissajous_test.lissajousGenerator_tester;
|
||||||
|
FOR ALL : lowpass USE ENTITY WaveformGenerator.lowpass;
|
||||||
|
-- pragma synthesis_on
|
||||||
|
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
-- Architecture concurrent statements
|
||||||
|
-- HDL Embedded Text Block 1 eb1
|
||||||
|
xParallel <= (others => xSerial);
|
||||||
|
yParallel <= (others => ySerial);
|
||||||
|
|
||||||
|
|
||||||
|
-- Instance port mappings.
|
||||||
|
I_DUT : lissajousGenerator
|
||||||
|
GENERIC MAP (
|
||||||
|
signalBitNb => signalBitNb,
|
||||||
|
phaseBitNb => phaseBitNb,
|
||||||
|
stepX => stepX,
|
||||||
|
stepY => stepY
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
clock => clock,
|
||||||
|
reset => reset,
|
||||||
|
triggerOut => triggerOut,
|
||||||
|
xOut => xSerial,
|
||||||
|
yOut => ySerial
|
||||||
|
);
|
||||||
|
I_tester : lissajousGenerator_tester
|
||||||
|
GENERIC MAP (
|
||||||
|
signalBitNb => signalBitNb,
|
||||||
|
clockFrequency => clockFrequency
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
triggerOut => triggerOut,
|
||||||
|
xLowapss => xLowapss,
|
||||||
|
xSerial => xSerial,
|
||||||
|
yLowpass => yLowpass,
|
||||||
|
ySerial => ySerial,
|
||||||
|
clock => clock,
|
||||||
|
reset => reset
|
||||||
|
);
|
||||||
|
I_filtX : lowpass
|
||||||
|
GENERIC MAP (
|
||||||
|
signalBitNb => signalBitNb,
|
||||||
|
shiftBitNb => lowpassShiftBitNb
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
lowpassOut => xLowapss,
|
||||||
|
clock => clock,
|
||||||
|
reset => reset,
|
||||||
|
lowpassIn => xParallel
|
||||||
|
);
|
||||||
|
I_filty : lowpass
|
||||||
|
GENERIC MAP (
|
||||||
|
signalBitNb => signalBitNb,
|
||||||
|
shiftBitNb => lowpassShiftBitNb
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
lowpassOut => yLowpass,
|
||||||
|
clock => clock,
|
||||||
|
reset => reset,
|
||||||
|
lowpassIn => yParallel
|
||||||
|
);
|
||||||
|
|
||||||
|
END struct;
|
||||||
@ -0,0 +1,31 @@
|
|||||||
|
-- VHDL Entity Lissajous_test.lissajousGenerator_tester.interface
|
||||||
|
--
|
||||||
|
-- Created:
|
||||||
|
-- by - axel.amand.UNKNOWN (WE7860)
|
||||||
|
-- at - 14:48:11 28.04.2023
|
||||||
|
--
|
||||||
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||||
|
--
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.all;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
ENTITY lissajousGenerator_tester IS
|
||||||
|
GENERIC(
|
||||||
|
signalBitNb : positive := 16;
|
||||||
|
clockFrequency : real := 60.0E6
|
||||||
|
);
|
||||||
|
PORT(
|
||||||
|
triggerOut : IN std_ulogic;
|
||||||
|
xLowapss : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
xSerial : IN std_ulogic;
|
||||||
|
yLowpass : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||||
|
ySerial : IN std_ulogic;
|
||||||
|
clock : OUT std_ulogic;
|
||||||
|
reset : OUT std_ulogic
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Declarations
|
||||||
|
|
||||||
|
END lissajousGenerator_tester ;
|
||||||
|
|
||||||
BIN
zz-solutions/04-Lissajous/Lissajous_test/hds/.cache.dat
Normal file
BIN
zz-solutions/04-Lissajous/Lissajous_test/hds/.cache.dat
Normal file
Binary file not shown.
@ -0,0 +1,12 @@
|
|||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW symbol.sb
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 50,0 8 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 11 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 1,0 12 0
|
||||||
@ -0,0 +1,211 @@
|
|||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 142,0 9 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 12
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 0,0 17 2
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1,0 20 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 20
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1562,0 29 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1554,0 30 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1827,0 31 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1695,0 32 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1697,0 33 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1693,0 34 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1744,0 35 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1762,0 36 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1683,0 37 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 38
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 39
|
||||||
|
LIBRARY Lissajous
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW struct
|
||||||
|
GRAPHIC 1594,0 41 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 14,0 42 1
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 49 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 428,0 50 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 88,0 51 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 93,0 52 0
|
||||||
|
DESIGN lissajous@generator
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 98,0 53 0
|
||||||
|
LIBRARY Lissajous_test
|
||||||
|
DESIGN lissajous@generator_tester
|
||||||
|
VIEW test
|
||||||
|
GRAPHIC 421,0 56 0
|
||||||
|
DESIGN lissajous@generator_tester
|
||||||
|
VIEW interface
|
||||||
|
GRAPHIC 14,0 57 1
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1829,0 62 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1665,0 63 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1687,0 64 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1738,0 65 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1637,0 66 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1564,0 67 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1556,0 68 0
|
||||||
|
LIBRARY WaveformGenerator
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW master@version
|
||||||
|
GRAPHIC 1612,0 71 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 14,0 72 1
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 57,0 77 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 52,0 78 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 76,0 79 0
|
||||||
|
DESIGN lowpass
|
||||||
|
VIEW symbol.sb
|
||||||
|
GRAPHIC 83,0 80 0
|
||||||
|
LIBRARY Lissajous_test
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 83
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1594,0 86 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 421,0 87 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1612,0 88 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 91
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1603,0 94 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 97
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
NO_GRAPHIC 98
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1594,0 100 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1601,0 101 1
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1564,0 108 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1556,0 109 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1829,0 110 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1687,0 111 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1637,0 112 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 421,0 114 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 428,0 115 1
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1612,0 128 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1619,0 129 1
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1665,0 134 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1659,0 135 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
|
VIEW struct.bd
|
||||||
|
GRAPHIC 1653,0 136 0
|
||||||
|
DESIGN lissajous@generator_test
|
||||||
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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@ -1280,6 +1280,7 @@ projectPaths [
|
|||||||
"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\04-Lissajous\\Prefs\\hds.hdp"
|
"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\04-Lissajous\\Prefs\\hds.hdp"
|
||||||
"C:\\work\\edu\\sem\\labo\\sem_labs\\04-Lissajous\\Prefs\\hds.hdp"
|
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|
||||||
"C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\hds.hdp"
|
"C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\hds.hdp"
|
||||||
|
"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\zz-solutions\\04-Lissajous\\Prefs\\hds.hdp"
|
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|
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|
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|
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||||||
name "Custom Paper Size10(215,9 x 279,4 mm)"
|
|
||||||
type 266
|
|
||||||
width 783
|
|
||||||
height 1013
|
|
||||||
)
|
|
||||||
]
|
]
|
||||||
exportPageSetupInfo (PageSetupInfo
|
exportPageSetupInfo (PageSetupInfo
|
||||||
ptrCmd "FrameMaker MIF"
|
ptrCmd "FrameMaker MIF"
|
||||||
@ -4292,7 +4071,7 @@ hdsWorkspaceLocation ""
|
|||||||
relativeLibraryRootDir ""
|
relativeLibraryRootDir ""
|
||||||
vmLabelLatestDontAskAgain 0
|
vmLabelLatestDontAskAgain 0
|
||||||
vmLabelWorkspaceDontAskAgain 0
|
vmLabelWorkspaceDontAskAgain 0
|
||||||
logWindowGeometry "600x619+-1073+193"
|
logWindowGeometry "600x619+255+144"
|
||||||
diagramBrowserTabNo 0
|
diagramBrowserTabNo 0
|
||||||
showInsertPortHint 0
|
showInsertPortHint 0
|
||||||
showContentFirstTime 0
|
showContentFirstTime 0
|
||||||
|
|||||||
6710
zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/hds_user_prefs.bak
Normal file
6710
zz-solutions/04-Lissajous/Prefs/hds_user/v2019.2/hds_user_prefs.bak
Normal file
File diff suppressed because it is too large
Load Diff
@ -16,8 +16,8 @@ set VERBOSE=1
|
|||||||
set REQUIRE_LIBS=0
|
set REQUIRE_LIBS=0
|
||||||
set REQUIRE_HDS=1
|
set REQUIRE_HDS=1
|
||||||
set REQUIRE_MODELSIM=1
|
set REQUIRE_MODELSIM=1
|
||||||
set REQUIRE_ISE=0
|
set REQUIRE_ISE=1
|
||||||
set REQUIRE_DIAMOND=1
|
set REQUIRE_DIAMOND=0
|
||||||
|
|
||||||
:: Set project name
|
:: Set project name
|
||||||
set design_name=%~n0
|
set design_name=%~n0
|
||||||
|
|||||||
BIN
zz-solutions/Libs/Lattice/hds/.cache.dat
Normal file
BIN
zz-solutions/Libs/Lattice/hds/.cache.dat
Normal file
Binary file not shown.
Loading…
Reference in New Issue
Block a user