add solutions

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order1_masterVersion.vhd

@@ -0,0 +1,29 @@
+ARCHITECTURE masterVersion OF DAC IS
+
+  signal parallelIn1: unsigned(parallelIn'range);
+  signal integrator: unsigned(parallelIn'high+1 downto 0);
+  signal quantized: std_ulogic;
+
+BEGIN
+
+--  parallelIn1 <= parallelIn;
+  parallelIn1 <= parallelIn/2 + 2**(parallelIn'length-2);
+
+  integrate: process(reset, clock)
+  begin
+    if reset = '1' then
+      integrator <= (others => '0');
+    elsif rising_edge(clock) then
+      if quantized = '0' then
+        integrator <= integrator + parallelIn1;
+      else
+        integrator <= integrator + parallelIn1 - 2**parallelIn'length;
+      end if;
+    end if;
+  end process integrate;
+
+  quantized <= integrator(integrator'high);
+
+  serialOut <= quantized;
+
+END ARCHITECTURE masterVersion;

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order1_studentVersion.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE studentVersion OF DAC IS
+BEGIN
+  serialOut <= '0';
+END ARCHITECTURE studentVersion;

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order2_masterVersion.vhd

@@ -0,0 +1,59 @@
+ARCHITECTURE order2_masterVersion OF DAC IS
+
+  constant attenuationShift: positive := 3;
+  constant acc1BitNb: positive := parallelIn'length+5;
+  constant acc2BitNb: positive := parallelIn'length+5;
+  signal parallelIn1, parallelIn2: signed(parallelIn'high downto 0);
+  signal acc1: signed(acc1BitNb-1 downto 0);
+  signal acc2: signed(acc2BitNb-1 downto 0);
+  constant c1: signed(acc1'range)
+    := shift_left(to_signed(1, acc1'length), parallelIn'length-1);
+  constant c2: signed(acc2'range)
+    := resize(shift_left(c1, 4), acc2'length);
+  signal quantized: std_ulogic;
+
+BEGIN
+  ------------------------------------------------------------------------------
+                                                -- offset input to signed values
+
+  parallelIn1(parallelIn1'high) <= not parallelIn(parallelIn'high);
+  parallelIn1(parallelIn1'high-1 downto 0) <= 
+    signed(parallelIn(parallelIn'high-1 downto 0));
+                                                             -- attenuate signal
+  parallelIn2 <= parallelIn1 - shift_right(parallelIn1, attenuationShift);
+
+  ------------------------------------------------------------------------------
+                                                               -- SD integrators
+  integrate1: process(reset, clock)
+  begin
+    if reset = '1' then
+      acc1 <= (others => '0');
+    elsif rising_edge(clock) then
+      if quantized = '1' then
+        acc1 <= acc1 + resize(parallelIn2, acc1'length) - c1;
+      else
+        acc1 <= acc1 + resize(parallelIn2, acc1'length) + c1;
+      end if;
+    end if;
+  end process integrate1;
+
+  integrate2: process(reset, clock)
+  begin
+    if reset = '1' then
+      acc2 <= (others => '0');
+    elsif rising_edge(clock) then
+      if quantized = '1' then
+        acc2 <= acc2 + resize(acc1, acc2'length) - c2;
+      else
+        acc2 <= acc2 + resize(acc1, acc2'length) + c2;
+      end if;
+    end if;
+  end process integrate2;
+
+  ------------------------------------------------------------------------------
+                                                  -- test last integrator output
+  quantized <= '1' when acc2 >= 0 else '0';
+  serialOut <= quantized;
+
+END ARCHITECTURE order2_masterVersion;
+

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order2_studentVersion.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE order2_studentVersion OF DAC IS
+BEGIN
+  serialOut <= '0';
+END ARCHITECTURE order2_studentVersion;

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/dac_entity.vhg

@@ -0,0 +1,27 @@
+-- VHDL Entity DigitalToAnalogConverter.DAC.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:06:08 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY DAC IS
+    GENERIC( 
+        signalBitNb : positive := 16
+    );
+    PORT( 
+        serialOut  : OUT    std_ulogic;
+        parallelIn : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        clock      : IN     std_ulogic;
+        reset      : IN     std_ulogic
+    );
+
+-- Declarations
+
+END DAC ;
+

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order1_masterVersion.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order1_studentVersion.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order2_masterVersion.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order2_studentVersion.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_dac_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_dac_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.xrf/dac_entity.xrf

@@ -0,0 +1,27 @@
+DESIGN @d@a@c
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN @d@a@c
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN @d@a@c
+VIEW symbol.sb
+GRAPHIC 13,0 13 1 
+DESIGN @d@a@c
+VIEW symbol.sb
+GRAPHIC 67,0 17 0 
+DESIGN @d@a@c
+VIEW symbol.sb
+GRAPHIC 57,0 18 0 
+DESIGN @d@a@c
+VIEW symbol.sb
+GRAPHIC 52,0 19 0 
+DESIGN @d@a@c
+VIEW symbol.sb
+GRAPHIC 76,0 20 0 
+DESIGN @d@a@c
+VIEW symbol.sb
+GRAPHIC 1,0 23 0 
+DESIGN @d@a@c
+VIEW symbol.sb
+GRAPHIC 1,0 24 0 

zz-solutions/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/_dac._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom masterVersion
+DEFAULT_FILE atom DAC_order1_masterVersion.vhd