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github-classroom[bot]
2024-02-23 13:01:05 +00:00
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commit d212040c30
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4
03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order1_studentVersion.vhd Normal file
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ARCHITECTURE studentVersion OF DAC IS
BEGIN
serialOut <= '0';
END ARCHITECTURE studentVersion;

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03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order2_studentVersion.vhd Normal file
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ARCHITECTURE order2_studentVersion OF DAC IS
BEGIN
serialOut <= '0';
END ARCHITECTURE order2_studentVersion;

1
03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order1_studentVersion.vhd._fpf Normal file
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DIALECT atom VHDL_2008

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03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order2_studentVersion.vhd._fpf Normal file
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DIALECT atom VHDL_2008

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03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_dac_entity.vhd._fpf Executable file
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DIALECT atom VHDL_2008

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03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_dac_entity.vhg._fpf Normal file
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DIALECT atom VHDL_2008

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03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/_dac._epf Normal file
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DEFAULT_ARCHITECTURE atom studentVersion
DEFAULT_FILE atom DAC_order1_studentVersion.vhd

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03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/DAC_tester_test.vhd Normal file
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library ieee;
use ieee.math_real.all;
ARCHITECTURE test OF DAC_tester IS
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal sClock: std_uLogic := '1';
signal sineFrequency: real := 20.0E3;
signal tReal: real := 0.0;
signal outAmplitude: real := 1.0;
signal outReal: real := 0.0;
signal outUnsigned: unsigned(parallelIn'range);
BEGIN
------------------------------------------------------------------------------
-- clock and reset
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
reset <= '1', '0' after 2*clockPeriod;
------------------------------------------------------------------------------
-- time signals
process(sClock)
begin
if rising_edge(sClock) then
tReal <= tReal + 1.0/clockFrequency;
end if;
end process;
outReal <= outAmplitude * ( sin(2.0*math_pi*sineFrequency*tReal) + 1.0) / 2.0;
outUnsigned <= to_unsigned(integer(outReal * real(2**(outUnsigned'length)-1)), outUnsigned'length);
parallelIn <= outUnsigned;
-- parallelIn <= shift_left(to_unsigned(1, parallelIn'length), parallelIn'length-1);
-- parallelIn <= shift_left(to_unsigned(3, parallelIn'length), parallelIn'length-2);
END ARCHITECTURE test;

1
03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_DAC_tester_test.vhd._fpf Normal file
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03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_dac_tb_entity.vhg._fpf Normal file
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03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_dac_tb_struct.vhg._fpf Normal file
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03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_dac_tester_entity.vhg._fpf Normal file
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03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/@d@a@c_tb/struct.bd Normal file
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03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/@d@a@c_tb/symbol.sb Normal file
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03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tb._epf Normal file
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DEFAULT_FILE atom @d@a@c_tb/struct.bd
DEFAULT_ARCHITECTURE atom struct
TOP_MARKER atom 1

2
03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tester._epf Normal file
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DEFAULT_ARCHITECTURE atom test
DEFAULT_FILE atom DAC_tester_test.vhd

31
03-DigitalToAnalogConverter/Prefs/hds.hdp Normal file
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[Concat]
[ModelSim]
DigitalToAnalogConverter = $SCRATCH_DIR/DigitalToAnalogConverter
DigitalToAnalogConverter_test = $SCRATCH_DIR/DigitalToAnalogConverter_test
SplineInterpolator = $SCRATCH_DIR/SplineInterpolator
SplineInterpolator_test = $SCRATCH_DIR/SplineInterpolator_test
WaveformGenerator = $SCRATCH_DIR/WaveformGenerator
WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test
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DigitalToAnalogConverter = $HDS_PROJECT_DIR/../DigitalToAnalogConverter/hdl
DigitalToAnalogConverter_test = $HDS_PROJECT_DIR/../DigitalToAnalogConverter_test/hdl
ieee = $HDS_HOME/hdl_libs/ieee/hdl
SplineInterpolator = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator/hdl
SplineInterpolator_test = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator_test/hdl
std = $HDS_HOME/hdl_libs/std/hdl
WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hdl
WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hdl
[hds]
DigitalToAnalogConverter = $HDS_PROJECT_DIR/../DigitalToAnalogConverter/hds
DigitalToAnalogConverter_test = $HDS_PROJECT_DIR/../DigitalToAnalogConverter_test/hds
ieee = $HDS_HOME/hdl_libs/ieee/hds
SplineInterpolator = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator/hds
SplineInterpolator_test = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator_test/hds
std = $HDS_HOME/hdl_libs/std/hds
WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hds
WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hds
[library_type]
ieee = standard
std = standard
[shared]
others = $HDS_TEAM_HOME/shared.hdp

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03-DigitalToAnalogConverter/Prefs/hds_team/shared.hdp Normal file
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std = $HDS_HOME/hdl_libs/std/hds
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verilog = $HDS_HOME/hdl_libs/verilog/hds
vital2000 = $HDS_HOME/hdl_libs/vital2000/hds
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synopsys = $HDS_HOME/hdl_libs/synopsys/hdl
verilog = $HDS_HOME/hdl_libs/verilog/hdl
vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl
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std = standard
synopsys = standard
verilog = standard
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55
03-DigitalToAnalogConverter/Prefs/hds_team/v2018.1/hds_team_prefs Normal file
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41
03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk Normal file
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03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk Normal file
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98
03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk Normal file
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162
03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk Normal file
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114
03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk Normal file
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13
03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt Normal file
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@ -0,0 +1,13 @@
FILE_NAMING_RULE: new_document.txt
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15
03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
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17
03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd Normal file
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@ -0,0 +1,17 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
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19
03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd Normal file
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@ -0,0 +1,19 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
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DESCRIPTION_END
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CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
END FOR;
END %(entity_name)_config;

15
03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd Normal file
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@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
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16
03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd Normal file
View File

@ -0,0 +1,16 @@
FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
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-- using Mentor Graphics HDL Designer(TM) %(version)
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PACKAGE BODY %(entity_name) IS
END %(entity_name);

18
03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd Normal file
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@ -0,0 +1,18 @@
FILE_NAMING_RULE: %(entity_name)_pkg.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Header files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Header %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE %(entity_name) IS
END %(entity_name);

6831
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/hds_user_prefs Normal file
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41
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/generate.tsk Normal file
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@ -0,0 +1,41 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Generate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp"
hasBitmap 1
tooltip "Performs generation of graphics files"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"Generator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 1
onPulldownMenu 1
onToolbar 1
enabled 1
hierDepth 2
)

98
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk Normal file
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@ -0,0 +1,98 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Compile"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp"
hasBitmap 1
tooltip "Runs ModelSim compilation"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"ModelSimCompiler"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"64bit"
"0"
"compAlways"
"0"
"covSwitch"
""
"coverNoSub"
""
"dontAskAgain"
"0"
"enableMFCU"
"1"
"excludePSL"
"0"
"exepath"
"$MODELSIM_HOME"
"logFile"
""
"logicalLib"
"1"
"mapAllLib"
"0"
"mapQuartusIPs"
"1"
"masterCov"
"0"
"peSe"
"EE"
"prevOnly"
"0"
"quartusSimDir"
"$HDS_PROJECT_DIR/QuartusIPSimLibs"
"replayScriptPath"
""
"saveReplayScript"
"0"
"server"
""
"showCmd"
"0"
"transcript"
"1"
"useFlatLibrary"
"0"
"useRemote"
"0"
"useShortName"
"0"
"vhdlSwitches"
" -nologo"
"vlogSwitches"
" -nologo"
]
)
]
PreferedTasks [
]
onShortcutBar 1
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
)

83
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk Normal file
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@ -0,0 +1,83 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "ModelSim Flow"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp"
hasBitmap 1
tooltip "Generate and run entire ModelSim flow"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
(preferedMap
preferedEnum 0
preferedSetting "$MODELSIM_HOME"
)
(preferedMap
preferedEnum 2
preferedSetting "ModelSim"
)
]
onShortcutBar 1
onPulldownMenu 1
onToolbar 1
enabled 1
hierDepth 1
subTasks [
(HDSTaskRef
TaskName "Generate"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
reffedTaskName "USER:Generate"
)
(HDSTaskRef
TaskName "ModelSim Compile"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
reffedTaskName "USER:ModelSim Compile"
)
(HDSTaskRef
TaskName "ModelSim Simulate"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
reffedTaskName "USER:ModelSim Simulate"
)
]
)

96
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk Normal file
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@ -0,0 +1,96 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Simulate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp"
hasBitmap 1
tooltip "Invokes the ModelSim Simulator"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"1"
"runMethod"
"gui"
"runnableObject"
"ModelSimSimulator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"Arguments"
""
"Arguments1"
"do controller.do"
"Arguments2"
"controller.do"
"Communication"
"1"
"DelaySelection"
"typ"
"GlitchGeneration"
"1"
"InitCmd"
"$SIMULATION_DIR\\IND.do"
"LogFile"
""
"RemoteHost"
""
"Resolution"
"ps"
"SdfDelay"
"typ"
"SdfMultiSrcDelay"
"latest"
"SdfReduce"
"0"
"SdfWarnings"
"1"
"TimingChecks"
"1"
"UseBatch"
"0"
"UseGUI"
"1"
"VitalVersion"
"95"
"autoNames"
"1"
"coverage"
"0"
"excludePSL"
"0"
"exepath"
"$MODELSIM_HOME"
"minimumSimSetting"
"0"
"saveReplayScript"
"0"
"useCustomSimDir"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 1
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)

162
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk Normal file
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@ -0,0 +1,162 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Prepare for Synthesis"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp"
hasBitmap 1
tooltip "generates a single file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 1
enabled 1
hierDepth 1
subTasks [
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Generate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp"
hasBitmap 1
tooltip "Performs generation of graphics files"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"Generator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Concatenate HDL"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp"
hasBitmap 1
tooltip "Appends all HDL files together"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"Concatenation"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"1"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"outputFileNameRoot"
"%(concat_file)"
"outputVerilogFileExtension"
"v"
"outputVhdlFileExtension"
"vhd"
"place"
"0"
"specifyDir"
""
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Trim libraries"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "comment out library declarations for singles file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd"
"captureOutput"
"1"
"customPrompt"
""
"initialDir"
"$CONCAT_DIR"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"$HDS_HOME\\resources\\perl\\bin\\perl.exe"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
]
)

163
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk Normal file
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@ -0,0 +1,163 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Xilinx Project Navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp"
hasBitmap 1
tooltip "Xilinx Flow"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
subTasks [
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Update.xise"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "Update file references in the Xilnx project .xise file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf"
"captureOutput"
"1"
"customPrompt"
""
"initialDir"
"$ISE_WORK_DIR"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"$HDS_HOME\\resources\\perl\\bin\\perl.exe"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Xilinx Project navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp"
hasBitmap 1
tooltip "Invokes the Xilinx ISE tool"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
"$DESIGN_NAME.xise"
"captureOutput"
"0"
"customPrompt"
""
"descriptiveName"
"FPGA Technology Setup Plugin"
"initialDir"
"$ISE_WORK_DIR"
"isHierarchical"
"0"
"needsSave"
"0"
"pluginInfo"
"FPGA Technology Setup Plug-in v2.0
For additional information, exceptions, compatibility issues and updates, visit SupportNet."
"pluginVersion"
"2.0"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"$ISE_HOME\\bin\\nt64\\ise.exe"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"InputFile"
"U:/ELN_board/Board/concat/cursor.vhd"
"RunFromPlugin"
"False"
"RunInteractiveFromPlugIn"
"True"
"createAsciiFile"
"False"
"createBinaryFile"
"False"
"createFiles"
"True"
"createScriptFile"
"False"
"device"
"xc2vp7"
"edifngcPath"
"U:/ELN_board/Board/concat/cursor.vhd"
"effortLevel"
"Standard"
"family"
"virtex2p"
"familyName"
"virtex2p"
"netlist"
"other"
"netlistDefaultView"
"True"
"package"
"fg456"
"simulationModelLanguage"
"Modelsim_VHDL"
"speed"
"-7"
"synthTool"
"Xilinx XST"
"ucfPath"
""
"vendor"
"xilinx"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
]
)

13
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt Normal file
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FILE_NAMING_RULE: new_document.txt
DESCRIPTION_START
This is the default template used for the creation of Text Document files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
#
# Created:
# by - %(user).%(group) (%(host))
# at - %(time) %(date)
#
# using Mentor Graphics HDL Designer(TM) %(version)
#

15
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd Normal file
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@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(architecture)

17
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd Normal file
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@ -0,0 +1,17 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)
--
%(architecture)

19
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd Normal file
View File

@ -0,0 +1,19 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Configuration %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
END FOR;
END %(entity_name)_config;

15
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd Normal file
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@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Entity %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)

16
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd Normal file
View File

@ -0,0 +1,16 @@
FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Body %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
PACKAGE BODY %(entity_name) IS
END %(entity_name);

18
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd Normal file
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@ -0,0 +1,18 @@
FILE_NAMING_RULE: %(entity_name)_pkg.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Header files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Header %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE %(entity_name) IS
END %(entity_name);

6842
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/hds_user_prefs Normal file
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162
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk Normal file
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@ -0,0 +1,162 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Diamond Project Navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp"
hasBitmap 1
tooltip "Diamond synthesis Flow"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
subTasks [
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Update.ldf"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "Update file references in the Diamond project .prjx file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
"$CONCAT_DIR\\..\\..\\Scripts\\update_diamond.pl $DESIGN_NAME.ldf $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.lpf"
"captureOutput"
"1"
"customPrompt"
""
"initialDir"
"$DIAMOND_WORK_DIR"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"$HDS_HOME\\resources\\perl\\bin\\perl.exe"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Diamond Project IDE"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp"
hasBitmap 1
tooltip "Invokes the Lattice Diamond tool"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
"$CONCAT_DIR\\..\\..\\Scripts\\start_diamond.pl $DESIGN_NAME.ldf"
"captureOutput"
"1"
"customPrompt"
""
"descriptiveName"
"FPGA Technology Setup Plugin"
"initialDir"
"$LIBERO_WORK_DIR"
"isHierarchical"
"0"
"needsSave"
"0"
"pluginInfo"
"FPGA Technology Setup Plug-in v2.0 For additional information, exceptions, compatibility issues and updates, visit SupportNet."
"pluginVersion"
"2.0"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"$HDS_HOME\\resources\\perl\\bin\\perl.exe"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"InputFile"
"U:/ELN_board/Board/concat/cursor.vhd"
"RunFromPlugin"
"False"
"RunInteractiveFromPlugIn"
"True"
"createAsciiFile"
"False"
"createBinaryFile"
"False"
"createFiles"
"True"
"createScriptFile"
"False"
"device"
"xc2vp7"
"edifngcPath"
"U:/ELN_board/Board/concat/cursor.vhd"
"effortLevel"
"Standard"
"family"
"virtex2p"
"familyName"
"virtex2p"
"netlist"
"other"
"netlistDefaultView"
"True"
"package"
"fg456"
"simulationModelLanguage"
"Modelsim_VHDL"
"speed"
"-7"
"synthTool"
"Xilinx XST"
"ucfPath"
""
"vendor"
"xilinx"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
]
)

41
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/generate.tsk Normal file
View File

@ -0,0 +1,41 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Generate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp"
hasBitmap 1
tooltip "Performs generation of graphics files"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"Generator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 1
onPulldownMenu 1
onToolbar 1
enabled 1
hierDepth 2
)

98
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk Normal file
View File

@ -0,0 +1,98 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Compile"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp"
hasBitmap 1
tooltip "Runs ModelSim compilation"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"ModelSimCompiler"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"64bit"
"0"
"compAlways"
"0"
"covSwitch"
""
"coverNoSub"
""
"dontAskAgain"
"0"
"enableMFCU"
"1"
"excludePSL"
"0"
"exepath"
"$MODELSIM_HOME"
"logFile"
""
"logicalLib"
"1"
"mapAllLib"
"0"
"mapQuartusIPs"
"1"
"masterCov"
"0"
"peSe"
"EE"
"prevOnly"
"0"
"quartusSimDir"
"$HDS_PROJECT_DIR/QuartusIPSimLibs"
"replayScriptPath"
""
"saveReplayScript"
"0"
"server"
""
"showCmd"
"0"
"transcript"
"1"
"useFlatLibrary"
"0"
"useRemote"
"0"
"useShortName"
"0"
"vhdlSwitches"
" -nologo"
"vlogSwitches"
" -nologo"
]
)
]
PreferedTasks [
]
onShortcutBar 1
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
)

83
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk Normal file
View File

@ -0,0 +1,83 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "ModelSim Flow"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp"
hasBitmap 1
tooltip "Generate and run entire ModelSim flow"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
(preferedMap
preferedEnum 0
preferedSetting "$MODELSIM_HOME"
)
(preferedMap
preferedEnum 2
preferedSetting "ModelSim"
)
]
onShortcutBar 1
onPulldownMenu 1
onToolbar 1
enabled 1
hierDepth 1
subTasks [
(HDSTaskRef
TaskName "Generate"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
reffedTaskName "USER:Generate"
)
(HDSTaskRef
TaskName "ModelSim Compile"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
reffedTaskName "USER:ModelSim Compile"
)
(HDSTaskRef
TaskName "ModelSim Simulate"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
reffedTaskName "USER:ModelSim Simulate"
)
]
)

98
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk Normal file
View File

@ -0,0 +1,98 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Simulate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp"
hasBitmap 1
tooltip "Invokes the ModelSim Simulator"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"1"
"runMethod"
"gui"
"runnableObject"
"ModelSimSimulator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"Arguments"
""
"Arguments1"
"do controller.do"
"Arguments2"
"controller.do"
"Communication"
"1"
"DelaySelection"
"typ"
"GlitchGeneration"
"1"
"InitCmd"
"$SIMULATION_DIR/DAC.do"
"LogFile"
""
"RemoteHost"
""
"Resolution"
"ps"
"SdfDelay"
"typ"
"SdfMultiSrcDelay"
"latest"
"SdfReduce"
"0"
"SdfWarnings"
"1"
"TimingChecks"
"1"
"UseBatch"
"0"
"UseCLI"
"0"
"UseGUI"
"1"
"VitalVersion"
"95"
"autoNames"
"1"
"coverage"
"0"
"excludePSL"
"0"
"exepath"
"$MODELSIM_HOME"
"minimumSimSetting"
"0"
"saveReplayScript"
"0"
"useCustomSimDir"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 1
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)

162
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk Normal file
View File

@ -0,0 +1,162 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Prepare for Synthesis"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp"
hasBitmap 1
tooltip "generates a single file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 1
enabled 1
hierDepth 1
subTasks [
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Generate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp"
hasBitmap 1
tooltip "Performs generation of graphics files"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"Generator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Concatenate HDL"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp"
hasBitmap 1
tooltip "Appends all HDL files together"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"Concatenation"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"1"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"outputFileNameRoot"
"%(concat_file)"
"outputVerilogFileExtension"
"v"
"outputVhdlFileExtension"
"vhd"
"place"
"0"
"specifyDir"
""
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Trim libraries"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "comment out library declarations for singles file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd"
"captureOutput"
"1"
"customPrompt"
""
"initialDir"
"$CONCAT_DIR"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"$HDS_HOME\\resources\\perl\\bin\\perl.exe"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
]
)

163
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk Normal file
View File

@ -0,0 +1,163 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Xilinx Project Navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp"
hasBitmap 1
tooltip "Xilinx Flow"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
subTasks [
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Update.xise"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "Update file references in the Xilnx project .xise file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf"
"captureOutput"
"1"
"customPrompt"
""
"initialDir"
"$ISE_WORK_DIR"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"$HDS_HOME\\resources\\perl\\bin\\perl.exe"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Xilinx Project navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp"
hasBitmap 1
tooltip "Invokes the Xilinx ISE tool"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
"$DESIGN_NAME.xise"
"captureOutput"
"0"
"customPrompt"
""
"descriptiveName"
"FPGA Technology Setup Plugin"
"initialDir"
"$ISE_WORK_DIR"
"isHierarchical"
"0"
"needsSave"
"0"
"pluginInfo"
"FPGA Technology Setup Plug-in v2.0
For additional information, exceptions, compatibility issues and updates, visit SupportNet."
"pluginVersion"
"2.0"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"$ISE_HOME\\bin\\nt64\\ise.exe"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"InputFile"
"U:/ELN_board/Board/concat/cursor.vhd"
"RunFromPlugin"
"False"
"RunInteractiveFromPlugIn"
"True"
"createAsciiFile"
"False"
"createBinaryFile"
"False"
"createFiles"
"True"
"createScriptFile"
"False"
"device"
"xc2vp7"
"edifngcPath"
"U:/ELN_board/Board/concat/cursor.vhd"
"effortLevel"
"Standard"
"family"
"virtex2p"
"familyName"
"virtex2p"
"netlist"
"other"
"netlistDefaultView"
"True"
"package"
"fg456"
"simulationModelLanguage"
"Modelsim_VHDL"
"speed"
"-7"
"synthTool"
"Xilinx XST"
"ucfPath"
""
"vendor"
"xilinx"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
]
)

13
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt Normal file
View File

@ -0,0 +1,13 @@
FILE_NAMING_RULE: new_document.txt
DESCRIPTION_START
This is the default template used for the creation of Text Document files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
#
# Created:
# by - %(user).%(group) (%(host))
# at - %(time) %(date)
#
# using Mentor Graphics HDL Designer(TM) %(version)
#

15
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(architecture)

17
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd Normal file
View File

@ -0,0 +1,17 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)
--
%(architecture)

19
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd Normal file
View File

@ -0,0 +1,19 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Configuration %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
END FOR;
END %(entity_name)_config;

15
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Entity %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)

16
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd Normal file
View File

@ -0,0 +1,16 @@
FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Body %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
PACKAGE BODY %(entity_name) IS
END %(entity_name);

18
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd Normal file
View File

@ -0,0 +1,18 @@
FILE_NAMING_RULE: %(entity_name)_pkg.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Header files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Header %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE %(entity_name) IS
END %(entity_name);

38
03-DigitalToAnalogConverter/Scripts/cleanGenerated.bash Executable file
View File

@ -0,0 +1,38 @@
#!/bin/bash
#================================================================================
# cleanGenerated.bash - Clean intermediate files form folder
#
base_directory="$(dirname "$(readlink -f "$0")")"
pushd $base_directory
base_directory="$base_directory/.."
SEPARATOR='--------------------------------------------------------------------------------'
INDENT=' '
echo "$SEPARATOR"
echo "-- ${0##*/} Started!"
echo ""
#-------------------------------------------------------------------------------
# Remove generated and cache files
#
find $base_directory -type f -name '.cache.dat' | xargs -r rm -v
find $base_directory -type f -name '*.bak' | xargs -r rm -v
find $base_directory -type f -name '*.lck' | xargs -r rm -v
find $base_directory -type f -name '*.vhd.info' | xargs -r rm -v
find $base_directory -type f -name 'default_view' | xargs -r rm -v
find $base_directory -type f -name '*_entity.vhd' | xargs -r rm -v
find $base_directory -type f -name '*_struct.vhd' | xargs -r rm -v
find $base_directory -type f -name '*_fsm.vhd' | xargs -r rm -v
find $base_directory -type f -name '*.vhg' | xargs -r rm -v
find $base_directory -type f -name '*.DS_Store' | xargs -r rm -v
find $base_directory -type d -name '.xrf' | xargs -r rm -Rv
#-------------------------------------------------------------------------------
# Exit
#
echo ""
echo "-- ${0##*/} Finished!"
echo "$SEPARATOR"
popd

42
03-DigitalToAnalogConverter/Scripts/cleanGenerated.bat Normal file
View File

@ -0,0 +1,42 @@
::==============================================================================
:: cleanGenerated.bat
:: Clean intermediate files from folder
::
:start
@echo off
setlocal
set cmd_location="%~dp0"
pushd %cmd_location%
set SEPARATOR="--------------------------------------------------------------------------------"
set INDENT=" "
echo %SEPARATOR%
echo "-- %~nx0 Started!"
echo.
::------------------------------------------------------------------------------
:: Delete intermediate files
::
set base_directory="%cmd_location:"=%.."
echo "Delete intermediate files in: %base_directory%"
del /f /s /a %base_directory%\*cache.dat
del /f /s /a %base_directory%\*.bak
del /f /s /a %base_directory%\*.lck
del /f /s /a %base_directory%\*.vhd.info
del /f /s /a %base_directory%\default_view
del /f /s /a %base_directory%\*_entity.vhd
del /f /s /a %base_directory%\*_struct.vhd
del /f /s /a %base_directory%\*_fsm.vhd
del /f /s /a %base_directory%\*.vhg
del /f /s /a %base_directory%\*.DS_Store
echo "Delete intermediate directories in: %base_directory%"
for /d /r "%base_directory:"=%\" %%a in (.xrf\) do if exist "%%a" rmdir /s /q "%%a"
:end
echo.
echo "-- %~nx0 Finished!"
echo %SEPARATOR%
popd
endlocal
goto:eof

39
03-DigitalToAnalogConverter/Scripts/cleanScratch.bat Normal file
View File

@ -0,0 +1,39 @@
::==============================================================================
:: cleanScratch.bat
:: Clean scratch directory
::
:start
@echo off
setlocal
set cmd_location="%~dp0"
pushd %cmd_location%
set SEPARATOR=--------------------------------------------------------------------------------
set INDENT=" "
echo %SEPARATOR%
echo -- %~nx0 Started!
echo.
::------------------------------------------------------------------------------
:: Delete scratch directory
::
if "%SCRATCH_DIR%" == "" (
set SCRATCH_DIR=C:\temp\eda\
)
echo Delete scratch directory %SCRATCH_DIR%
if exist %SCRATCH_DIR% (
echo Scratch directory found, deleting!
rmdir /S /Q "%SCRATCH_DIR%"
) else (
echo Scratch directory not found!
)
:end
echo.
echo -- %~nx0 Finished!
echo %SEPARATOR%
echo. && echo.
popd
endlocal
goto:eof

42
03-DigitalToAnalogConverter/Scripts/generateSSHKey.bash Normal file
View File

@ -0,0 +1,42 @@
#!/bin/bash
#==============================================================================
# generates an SSH key under default user location ~/.ssh/
# and add the public key to the clipboard
#
# the email could be given when calling the script or be prompted later
email=''
filename=$(hostname)
user=$(whoami)
usage='Usage: generateSSH.bash [-e email]'
# handle options
while getopts 'e:v' flag; do
case "${flag}" in
e) email=${OPTARG};;
esac
done
# if the mail is not given, prompt it
if [ -z "$email" ]
then
echo -n "Please enter your mail: "
read email
fi
# generates the key-couple
# cat /dev/zero create an empty file to be filled by the key
# then ssh-keygen is called with:
# -q to call it silently (no verbose)
# -N with empty string to set no-password
# -t to specify the type of key
# -C to set the user mail
cat /dev/zero | ssh-keygen -q -N "" -t ed25519 -C "${user}@${filename}" -f ~/.ssh/$filename
# then copy the public key into the clipboard
clip < ~/.ssh/${filename}.pub
# print output for user
echo -e "\nThe keyfiles are generated under ~/.ssh/"
echo -e "\nThe public key is in your clipboard, ready to be added to your Github account."

154
03-DigitalToAnalogConverter/Scripts/hdlDesigner.bash Executable file
View File

@ -0,0 +1,154 @@
#!/bin/bash
#================================================================================
# hdl_designer.bash - Starts HDL designer
#
base_directory="$(dirname "$(readlink -f "$0")")"
base_directory="$base_directory/.."
pushd $base_directory
SEPARATOR='--------------------------------------------------------------------------------'
INDENT=' '
echo "$SEPARATOR"
echo "-- ${0##*/} Started!"
echo ""
#--------------------------------------------------------------------------------
# Parse command line options
#
command_switches='n:d:p:m:i:u:t:s:c:y:vh'
usage='Usage: hdl_designer.bash [-v] [-h]'
usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]"
# set name and base directory
design_name=`basename $0 .bash`
design_directory=`dirname ${BASH_SOURCE[0]}`
while getopts $command_switches options; do
case $options in
n ) design_name=$OPTARG;;
d ) design_directory=$OPTARG;;
esac
done
# continue with preferences directory
prefs_directory="$design_directory/Prefs"
OPTIND=1
while getopts $command_switches options; do
case $options in
n ) design_name=$OPTARG;;
d ) design_directory=$OPTARG;;
p ) prefs_directory=$OPTARG;;
esac
done
# finish with other parameters
library_matchings="$design_name.hdp"
library_matchings='hds.hdp'
simulation_directory="$design_directory/Simulation"
user_prefs_directory="$prefs_directory/hds_user-linux"
team_prefs_directory="$prefs_directory/hds_team"
scratch_directory='/tmp/eda/'
synthesis_subdirectory="Board/ise"
concat_directory="$design_directory/Board/concat"
OPTIND=1
while getopts $command_switches options; do
case $options in
n ) ;;
d ) ;;
m ) library_matchings=$OPTARG;;
i ) simulation_directory=$OPTARG;;
u ) user_prefs_directory=$OPTARG;;
t ) team_prefs_directory=$OPTARG;;
s ) scratch_directory=$OPTARG;;
c ) concat_directory=$OPTARG;;
y ) synthesis_subdirectory=$OPTARG;;
v ) verbose=1;;
h ) echo -e $usage
exit 1;;
* ) echo -e $usage
exit 1;;
esac
done
design_directory=`realpath $design_directory`
library_matchings=`realpath $prefs_directory/$library_matchings`
simulation_directory=`realpath $simulation_directory`
user_prefs_directory=`realpath $user_prefs_directory`
team_prefs_directory=`realpath $team_prefs_directory`
concat_directory=`realpath $concat_directory`
mkdir -p $scratch_directory
scratch_directory=`realpath $scratch_directory`
#================================================================================
# Main script
#
#-------------------------------------------------------------------------------
# System environment variables
#
export HDS_HOME=/usr/opt/HDS
export MODELSIM_HOME=/usr/opt/Modelsim/modeltech/bin/
export SYNTHESIS_HOME=/usr/opt/Xilinx/ISE_DS/ISE
export LC_ALL=C
export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin
export MGLS_HOME=/usr/opt/HDS/license/mgls
#-------------------------------------------------------------------------------
# Project environment variables
#
export DESIGN_NAME=$design_name
export HDS_LIBS=$library_matchings
export HDS_USER_HOME="$user_prefs_directory"
export HDS_TEAM_HOME=$team_prefs_directory
export SIMULATION_DIR=$simulation_directory
export SCRATCH_DIR=$scratch_directory
export CONCAT_DIR=$concat_directory
export SYNTHESIS_BASE_DIR=`realpath $design_directory/$synthesis_subdirectory`
export SYNTHESIS_WORK_DIR=$scratch_directory/$synthesis_subdirectory
#-------------------------------------------------------------------------------
# Display info
#
if [ -n "$verbose" ] ; then
echo "Environment variables:"
echo "${INDENT}Design name is $DESIGN_NAME"
echo "${INDENT}Lib matchings file is $HDS_LIBS"
echo "${INDENT}Simulation directory is $SIMULATION_DIR"
echo "${INDENT}User prefs directory is $HDS_USER_HOME"
echo "${INDENT}Team prefs directory is $HDS_TEAM_HOME"
echo "${INDENT}Scratch directory is $SCRATCH_DIR"
echo "${INDENT}Concat directory is $CONCAT_DIR"
echo "${INDENT}HDS location is $HDS_HOME"
echo "${INDENT}Modelsim location is $MODELSIM_HOME"
echo "${INDENT}Synthesis app location is $SYNTHESIS_HOME"
echo "${INDENT}Synthesis base directory is $SYNTHESIS_BASE_DIR"
echo "${INDENT}Synthesis work directory is $SYNTHESIS_WORK_DIR"
fi
#-------------------------------------------------------------------------------
# Copy synthesis data to scratch
#
if true; then
echo "Copying"
echo "${INDENT}$SYNTHESIS_BASE_DIR"
echo "${INDENT}-> $SYNTHESIS_WORK_DIR"
fi
if [ -e "$SYNTHESIS_BASE_DIR" ]; then
rm -Rf $SYNTHESIS_WORK_DIR
mkdir -p $SYNTHESIS_WORK_DIR
cp -pr $SYNTHESIS_BASE_DIR/* $SYNTHESIS_WORK_DIR/
fi
#-------------------------------------------------------------------------------
# Launch application
#
hdl_designer &
#-------------------------------------------------------------------------------
# Exit
#
echo ""
echo "-- ${0##*/} Finished!"
echo "$SEPARATOR"
popd

301
03-DigitalToAnalogConverter/Scripts/hdlDesigner.bat Normal file
View File

@ -0,0 +1,301 @@
::==============================================================================
:: hdl_designer.bash - Starts HDL designer
::
:start
setlocal EnableExtensions EnableDelayedExpansion
set cmd_location=%~dp0
pushd %cmd_location%
set SEPARATOR=--------------------------------------------------------------------------------
set INDENT=" "
echo %SEPARATOR%
echo -- %~nx0 Started!
echo.
:: -----------------------------------------------------------------------------
:: Define default environment variables
IF NOT DEFINED REQUIRE_LIBS SET "REQUIRE_LIBS=0"
IF NOT DEFINED REQUIRE_HDS SET "REQUIRE_HDS=0"
IF NOT DEFINED REQUIRE_MODELSIM SET "REQUIRE_MODELSIM=0"
IF NOT DEFINED REQUIRE_ISE SET "REQUIRE_ISE=0"
IF NOT DEFINED REQUIRE_LIBERO SET "REQUIRE_LIBERO=0"
IF NOT DEFINED REQUIRE_DIAMOND SET "REQUIRE_DIAMOND=0"
IF NOT DEFINED REQUIRE_ICECUBE2 SET "REQUIRE_ICECUBE2=0"
::
::remove trailing backslash
if %cmd_location:~-1%==\ set design_directory=%design_directory:~0,-1%
set design_name=%~n0
set hpd_name=hds
if "%ISE_VERSION%"== "" (
set ISE_VERSION=14.7
)
set prefs_directory="%design_directory:"=%\Prefs"
set library_matchings="%hpd_name%.hdp"
set simulation_directory="%design_directory:"=%\Simulation"
set user_prefs_directory="%prefs_directory:"=%\hds_user"
set team_prefs_directory="%prefs_directory:"=%\hds_team"
if "%SCRATCH_DIR%" == "" (
set scratch_directory=C:\temp\eda\%username%
) else (
set scratch_directory=%SCRATCH_DIR%
)
set synthesis_subdirectory=""
if %REQUIRE_ISE% == 1 (
set synthesis_subdirectory="Board\ise"
)
if %REQUIRE_LIBERO% == 1 (
set synthesis_subdirectory="Board\libero"
)
if %REQUIRE_DIAMOND% == 1 (
set synthesis_subdirectory="Board\diamond"
)
if %REQUIRE_ICECUBE2% == 1 (
set synthesis_subdirectory="Board\icecube2"
)
set concat_directory="%design_directory:"=%\Board\concat"
::------------------------------------------------------------------------------
:: Parse command line options
::
:parse
set usage1="Usage: hdl_designer.bat [-v] [-h]"
set usage2=" [-n designName] [-d designDirectory]"
set usage3=" [-p prefsDirectory] [-u userPrefsDirectory] [-t teamPrefsDirectory]"
set usage4=" [-s scratchDirectory] [-c concatDirectory]"
set usage5=" [-y synthesisDirectory] [-m library_matchings]"
echo Search Commandline Parameters
:parseloop
if not "%1"=="" (
if "%1"=="-v" (
set VERBOSE=1
echo %INDENT:"=%verbose enabled
shift
)
if "%1"=="-h" (
goto :HELP
shift
)
if "%1"=="-n" (
set design_name=%2
echo %INDENT:"=%design_name=!design_name:"=!
shift & shift
)
if "%1"=="-d" (
set design_directory=%2
echo %INDENT:"=%design_directory=!design_directory:"=!
shift & shift
)
if "%1"=="-p" (
set prefs_directory=%2
echo %INDENT:"=%prefs_directory=!prefs_directory:"=!
shift & shift
)
if "%1"=="-u" (
set user_prefs_directory=%2
echo %INDENT:"=%user_prefs_directory=%user_prefs_directory:"=%
shift & shift
)
if "%1"=="-t" (
set team_prefs_directory=%2
echo %INDENT:"=%team_prefs_directory=%team_prefs_directory:"=%
shift & shift
)
if "%1"=="-s" (
set scratch_directory=%2
echo %INDENT:"=%scratch_directory=%scratch_directory:"=%
shift & shift
)
if "%1"=="-c" (
set concat_directory=%2
echo "%INDENT:"=%concat_directory=%concat_directory:"=% "
shift & shift
)
if "%1"=="-y" (
set synthesis_subdirectory=%2
echo %INDENT:"=%synthesis_subdirectory=%synthesis_subdirectory:"=%
shift & shift
)
if "%1"=="-m" (
set set library_matchings="%2.hdp"
echo %INDENT:"=%library_matchings=%library_matchings:"=%
shift & shift
)
goto :parseloop
)
echo.
:: Setting all concurrent variables
set prefs_directory="!design_directory:"=!\Prefs"
set user_prefs_directory="!prefs_directory:"=!\hds_user"
set team_prefs_directory="!prefs_directory:"=!\hds_team"
set library_matchings=!prefs_directory:"=!\!library_matchings:"=!
set simulation_directory="!design_directory:"=!\Simulation"
set concat_directory="!design_directory:"=!\Board\concat"
:: Getting realpath
:: TODO
:: create scratch dir
if not exist "%scratch_directory%" (
mkdir "%scratch_directory:"=%"
)
::================================================================================
:: Main script
::
echo.
call "./searchPaths.bat"
::------------------------------------------------------------------------------
:: Project environment variables
::
set DESIGN_NAME=%design_name:"=%
set HDS_LIBS=%library_matchings:"=%
set HDS_USER_HOME=%user_prefs_directory:"=%
set HDS_TEAM_HOME=%team_prefs_directory:"=%
set SIMULATION_DIR=%simulation_directory:"=%
:: Changing Slashed (Needed for Modelsim)
set SIMULATION_DIR=%SIMULATION_DIR:\=/%
set SCRATCH_DIR=%scratch_directory:"=%
set CONCAT_DIR=%concat_directory:"=%
set ISE_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=%
set ISE_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=%
set LIBERO_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=%
set LIBERO_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=%
set DIAMOND_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=%
set DIAMOND_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=%
set ICECUBE2_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=%
set ICECUBE2_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=%
::------------------------------------------------------------------------------
:: Display info
::
if !VERBOSE! == 1 (
echo Program Parameters
echo %INDENT:"=%DESIGN_NAME is %DESIGN_NAME:"=%
echo %INDENT:"=%HEI_LIBS_DIR is %HEI_LIBS_DIR:"=%
echo %INDENT:"=%HDS_LIBS is %HDS_LIBS:"=%
echo %INDENT:"=%SIMULATION_DIR is %SIMULATION_DIR:"=%
echo %INDENT:"=%HDS_USER_HOME is %HDS_USER_HOME:"=%
echo %INDENT:"=%HDS_TEAM_HOME is %HDS_TEAM_HOME:"=%
echo %INDENT:"=%SCRATCH_DIR is %SCRATCH_DIR:"=%
echo %INDENT:"=%CONCAT_DIR is %CONCAT_DIR:"=%
if %REQUIRE_HDS% == 1 (
echo %INDENT:"=%HDS_HOME is %HDS_HOME:"=%
)
if %REQUIRE_MODELSIM% == 1 (
echo %INDENT:"=%MODELSIM_HOME is %MODELSIM_HOME:"=%
)
if %REQUIRE_ISE% == 1 (
echo %INDENT:"=%ISE_HOME is %ISE_HOME:"=%
echo %INDENT:"=%ISE_BASE_DIR is %ISE_BASE_DIR:"=%
echo %INDENT:"=%ISE_WORK_DIR is %ISE_WORK_DIR:"=%
)
if %REQUIRE_LIBERO% == 1 (
echo %INDENT:"=%LIBERO_HOME is %LIBERO_HOME:"=%
echo %INDENT:"=%LIBERO_BASE_DIR is %LIBERO_BASE_DIR:"=%
echo %INDENT:"=%LIBERO_WORK_DIR is %LIBERO_WORK_DIR:"=%
)
if %REQUIRE_DIAMOND% == 1 (
echo %INDENT:"=%DIAMOND_HOME is %DIAMOND_HOME:"=%
echo %INDENT:"=%DIAMOND_BASE_DIR is %DIAMOND_BASE_DIR:"=%
echo %INDENT:"=%DIAMOND_WORK_DIR is %DIAMOND_WORK_DIR:"=%
)
if %REQUIRE_ICECUBE2% == 1 (
echo %INDENT:"=%ICECUBE2_HOME is %ICECUBE2_HOME:"=%
echo %INDENT:"=%ICECUBE2_BASE_DIR is %ICECUBE2_BASE_DIR:"=%
echo %INDENT:"=%ICECUBE2_WORK_DIR is %ICECUBE2_WORK_DIR:"=%
)
echo.
)
::------------------------------------------------------------------------------
:: Delete scratch directory
::
echo.
call "./cleanScratch.bat"
::------------------------------------------------------------------------------
:: Copy synthesis data to scratch directory
::
if %REQUIRE_ISE% == 1 (
if exist %ISE_BASE_DIR% (
echo %ISE_BASE_DIR:"=%
echo -> %ISE_WORK_DIR:"=%
if exist %ISE_WORK_DIR% (
rmdir /S /Q "%ISE_WORK_DIR%"
)
mkdir "%ISE_WORK_DIR%"
xcopy /Y "%ISE_BASE_DIR%" "%ISE_WORK_DIR%\"
)
)
if %REQUIRE_LIBERO% == 1 (
if exist %LIBERO_BASE_DIR% (
echo %LIBERO_BASE_DIR:"=%
echo -> %LIBERO_BASE_DIR:"=%
if exist %LIBERO_WORK_DIR% (
rmdir /S /Q "%LIBERO_WORK_DIR%"
)
mkdir "%LIBERO_WORK_DIR%"
xcopy /S /Y "%LIBERO_BASE_DIR%" "%LIBERO_WORK_DIR%\"
)
)
if %REQUIRE_DIAMOND% == 1 (
if exist %DIAMOND_BASE_DIR% (
echo %DIAMOND_BASE_DIR:"=%
echo -> %DIAMOND_BASE_DIR:"=%
if exist %DIAMOND_WORK_DIR% (
rmdir /S /Q "%DIAMOND_WORK_DIR%"
)
mkdir "%DIAMOND_WORK_DIR%"
xcopy /S /Y "%DIAMOND_BASE_DIR%" "%DIAMOND_WORK_DIR%\"
)
)
if %REQUIRE_ICECUBE2% == 1 (
if exist %ICECUBE2_BASE_DIR% (
echo %ICECUBE2_BASE_DIR:"=%
echo -> %ICECUBE2_BASE_DIR:"=%
if exist %ICECUBE2_WORK_DIR% (
rmdir /S /Q "%ICECUBE2_WORK_DIR%"
)
mkdir "%ICECUBE2_WORK_DIR%"
xcopy /S /Y "%ICECUBE2_BASE_DIR%" "%ICECUBE2_WORK_DIR%\"
)
)
::------------------------------------------------------------------------------
:: Launch application
::
echo -- Launching program
::echo %INDENT:"=%Waiting until programs finished...
::start /wait !HDS_HOME:"=!\bin\hdldesigner.exe
%windir%\system32\cmd.exe /c start !HDS_HOME!\bin\hdldesigner.exe
::echo -- Finished... YOU CAN CLOSE THIS WINDOW NOW!
:end
echo.
echo -- %~nx0 Finished!
echo %SEPARATOR%
echo. && echo.
popd
endlocal
goto:eof
::------------------------------------------------------------------------------
:: Helper Functions
::
:HELP
echo.
echo %usage1:"=%
echo %usage2:"=%
echo %usage3:"=%
echo %usage4:"=%
echo %usage5:"=%
echo.&pause&goto:eof

209
03-DigitalToAnalogConverter/Scripts/searchPaths.bat Normal file
View File

@ -0,0 +1,209 @@
::==============================================================================
:: search_paths.bat - Search for Libraries and HDL Tools
::
:start
@echo off
set cmd_location="%~dp0"
pushd %cmd_location%
set SEPARATOR=--------------------------------------------------------------------------------
set INDENT=" "
echo %SEPARATOR%
echo -- %~nx0 Started!
echo.
echo Search HEI Library
::------------------------------------------------------------------------------
:: Search HEI library directory
::
if !REQUIRE_LIBS! == 1 (
if "%HEI_LIBS_DIR%" == "" (
set HEI_LIBS_DIR=%design_directory:"=!%\Libs
if not exist !HEI_LIBS_DIR!\ (
:: check at folder one level above project folder, as used on svn for boards libraries
set HEI_LIBS_DIR=%design_directory:"=!%\..\Libs
if not exist !HEI_LIBS_DIR!\ (
:: check at folder one level above project folder, as used on svn for boards libraries
set HEI_LIBS_DIR=%design_directory:"=!%\..\..\Libs
if not exist !HEI_LIBS_DIR!\ (
:: check on server, as used for ET labs
set HEI_LIBS_DIR=R:\ETE\Ele1_8132\ELN\Labs\Libraries
if not exist !HEI_LIBS_DIR!\ (
:: check on server, as used for SI labs
set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries
if not exist !HEI_LIBS_DIR!\ (
echo "ERROR: No valid libraries found: please verify your project setup."
pause&goto:end
)
)
)
)
)
)
if exist !HEI_LIBS_DIR!\ (
echo %INDENT:"=%Found HEI_LIBS_DIR at !HEI_LIBS_DIR:"=!
) else (
echo %INDENT:"=%ERROR: No valid HEI_LIBS_DIR found: please verify your HEI_LIBS_DIR settings.
pause&goto:eof
)
)
echo Search Design Tools: HDL Designer, Modelsim, Xilinx ISE, Microsemi Libero, Lattice Diamond, Lattice IceCube2
::------------------------------------------------------------------------------
:: Search HDL Designer directory
::
if !REQUIRE_HDS! == 1 (
if "%HDS_HOME%" == "" (
set HDS_HOME=C:\eda\MentorGraphics\HDS
if not exist !HDS_HOME!\ (
set HDS_HOME=C:\tools\eda\HDS
if not exist !HDS_HOME!\ (
echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings.
pause&goto:eof
)
)
)
if exist !HDS_HOME! (
echo %INDENT:"=%Found HDL-Designer at !HDS_HOME!
) else (
echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings.
pause&goto:eof
)
)
::------------------------------------------------------------------------------
:: Search Modelsim directory
::
if !REQUIRE_MODELSIM! == 1 (
if "%MODELSIM_HOME%" == "" (
set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win64
if not exist !MODELSIM_HOME!\ (
set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win32
if not exist !MODELSIM_HOME!\ (
set MODELSIM_HOME=C:\tools\eda\Modelsim\win64
if not exist !MODELSIM_HOME!\ (
set MODELSIM_HOME=C:\tools\eda\Modelsim\win32
if not exist !MODELSIM_HOME!\ (
echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings.
pause&goto:eof
)
)
)
)
)
if exist !MODELSIM_HOME! (
echo %INDENT:"=%Found ModelSim at !MODELSIM_HOME:"=!
) else (
echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings.
pause
goto:eof
)
)
::------------------------------------------------------------------------------
:: Search Xilinx ISE directory
::
if !REQUIRE_ISE! == 1 (
if "%ISE_HOME%" == "" (
set ISE_HOME=C:\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE
if not exist !ISE_HOME!\ (
set ISE_HOME=C:\tools\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE
if not exist !ISE_HOME!\ (
echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings.
pause&goto:eof
)
)
)
if exist !ISE_HOME! (
echo %INDENT:"=%Found ISE at !ISE_HOME:"=!
) else (
echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings.
pause&goto:eof
)
)
::------------------------------------------------------------------------------
:: Search Microsemi Libero directory
::
if %REQUIRE_LIBERO% == 1 (
if "%LIBERO_HOME%" == "" (
set LIBERO_HOME=C:\eda\Microsemi\Libero
if not exist !LIBERO_HOME!\ (
set LIBERO_HOME=C:\tools\eda\Microsemi\Libero
if not exist !LIBERO_HOME!\ (
echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings.
pause&goto:eof
)
)
)
if exist !LIBERO_HOME! (
echo %INDENT:"=%Found Libero at !LIBERO_HOME:"=!
) else (
echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings.
pause
goto:eof
)
)
::------------------------------------------------------------------------------
:: Search Lattice Diamond directory
::
if %REQUIRE_DIAMOND% == 1 (
if "%DIAMOND_HOME%" == "" (
set DIAMOND_HOME=C:\eda\lscc\diamond\3.12
if not exist !DIAMOND_HOME!\ (
set DIAMOND_HOME=C:\tools\eda\lscc\diamond\3.12
if not exist !DIAMOND_HOME!\ (
set DIAMOND_HOME=C:\lscc\diamond\3.12
if not exist !DIAMOND_HOME!\ (
echo %INDENT:"=%ERROR: No valid installation of Lattice Diamond found - please verify your DIAMOND_HOME settings.
pause&goto:eof
)
)
)
)
if exist !DIAMOND_HOME! (
echo %INDENT:"=%Found Diamond at !DIAMOND_HOME:"=!
) else (
echo %INDENT:"=%ERROR: No valid installation of Diamond found - please verify your DIAMOND_HOME settings.
pause
goto:eof
)
)
::------------------------------------------------------------------------------
:: Search Lattice IceCube2 directory
::
if %REQUIRE_ICECUBE2% == 1 (
if "%ICECUBE2_HOME%" == "" (
set ICECUBE2_HOME=C:\eda\lscc\iCEcube2.2020.12
if not exist !ICECUBE2_HOME!\ (
set ICECUBE2_HOME=C:\tools\eda\lscc\iCEcube2.2020.12
if not exist !ICECUBE2_HOME!\ (
set ICECUBE2_HOME=C:\lscc\iCEcube2.2020.12
if not exist !ICECUBE2_HOME!\ (
echo %INDENT:"=%ERROR: No valid installation of Lattice IceCube2 found - please verify your ICECUBE2_HOME settings.
pause&goto:eof
)
)
)
)
if exist !ICECUBE2_HOME! (
echo %INDENT:"=%Found IceCube2 at !ICECUBE2_HOME:"=!
) else (
echo %INDENT:"=%ERROR: No valid installation of IceCube2 found - please verify your ICECUBE2_HOME settings.
pause
goto:eof
)
)
:end
echo.
echo -- %~nx0 Finished!
echo %SEPARATOR%
echo. && echo.
popd
goto:eof

170
03-DigitalToAnalogConverter/Scripts/trimLibs.pl Normal file
View File

@ -0,0 +1,170 @@
#!/usr/bin/perl
# ------------------------------------------------------------------------------
# trimLibs
# Comment regular libraries in an concatenated file
# Help Parameter : <?>
# Parameter : trimlibs.pl <Input File Name> <Output File Name>
# ------------------------------------------------------------------------------
# Authors:
# cof: [Fran<61>ois Corthay](francois.corthay@hevs.ch)
# guo: [Oliver A. Gubler](oliver.gubler@hevs.ch)
# zas: [Silvan Zahno](silvan.zahno@hevs.ch)
# gal: [Laurent Gauch]
# ama: [Amand Axel](axel.amand@hevs.ch)
# ------------------------------------------------------------------------------
# Changelog:
# 2023.05.16 : ama
# * Add: ice40 libs support
# 2023.02.01 : ama
# * Add: ECP5U libs support
# 2019.08.23 : cof
# * Comment "omment "FOR xxxx : yyy USE ENTITY zzz;"" instead all "For All ... work" lines
# * Seen problems in ELN_Kart
# 2019.06.11 : zas
# * Comment "For All .... work."" instead all "For All" lines
# * Allow Outputfilename as Env var or as Script parameter
# 2015-08-25 : guo
# * added unisim to the list of excluded libraries
# 2015-05-08 : guo
# * added verbosity debug
# * changed this header
# * minor comment modifications
# 2013-08-13 : zas guo
# Handle error if environment variable not found, character'pos('$') -> ')
# was found as env var, added exception
# 2013-06-13 : cof zas guo
# Remove comments from testline
# 2013-01-09 : cof --
# * Bugfix: no carriage return on commented "use" statements
# * Bugfix: more precise targeting of "library" statement
# * Bugfix: "Library" test after "use" test
# 2012-04-27 : zas
# * Bugfix: on feature added in version 2011-06-10
# 2012-02-02 : zas
# * Write the output into a new file with the name defined in the
# * $DESIGN_NAME variable
# 2012-01-23 : zas
# * Replaces $env_var_name by the value of the found environmemnt variable.
# * Mostly used to replace $SIMULATION_DIR for initialise bram's from a file
# * placed in the Simulation Directory
# 2011-06-10 : zas
# Replaces
# library xxx;use xxx.yyy.all;
# with
# --library xxx;
# use work.yyy.all;
# 2005...2011 : cof
# Improvements
# 2005-01-29 : gal
# initlial release
# ------------------------------------------------------------------------------
$separator = '-' x 79;
$indent = ' ' x 2;
$hdlInFileSpec = $ARGV[0];
if (defined $ARGV[1]) {
$hdlOutFileSpec = $ARGV[1];
}
else {
$hdlOutFileSpec = 'trimmed.vhd';
}
$verbose = 1;
$debug = 0;
#-------------------------------------------------------------------------------
# program I/O files
#
$tempFileSpec = $hdlOutFileSpec . '.tmp';
if ($verbose == 1) {
print "\n$separator\n";
print "Trimming library declarations from $hdlInFileSpec to $hdlOutFileSpec\n";
print $indent, "temporary file spec: $tempFileSpec\n";
}
#-------------------------------------------------------------------------------
# read original file, edit and save to temporary file
#
my $line;
open(HDLFile, $hdlInFileSpec) || die "couldn't open $HDLFileSpec!";
open(tempFile, ">$tempFileSpec");
while (chop($line = <HDLFile>)) {
# remove all comment for the test
my $testline = $line;
$testline =~ s/--.*//;
# Replace 'use xxx.yyy' with 'use work.yyy', except if xxx is ieee or std or unisim or ecp5u or ice40
if ($testline =~ m/use\s.*\.all\s*;/i) {
if ( not($testline =~ m/\bieee\./i) and
not($testline =~ m/\bstd\./i) and
not($testline =~ m/\bunisim\./i) and
not($testline =~ m/\becp5u\./i) and
not($testline =~ m/ice40.*\./i)) {
# if there is any char before "use" except \s, insert new line \n
if ( ($testline =~ m/[^\s]\s*use/i) ) {
$line =~ s/use\s+.*?\./\nuse work./i;
if ($debug == 1) {
print "TEST0099: ", $testline, "\n"
}
}
else {
$line =~ s/use\s+.*?\./use work./i;
if ($debug == 1) {
print "TEST0105: ", $testline, "\n"
}
}
}
}
# Comment libraries which aren't ieee or std or unisim or ecp5u or ice40
if (($testline =~ m/\slibrary\s+/i) or ($testline =~ m/\Alibrary\s+/i)) {
if ( not($testline =~ m/ieee/i) and
not($testline =~ m/std/i) and
not($testline =~ m/unisim/i) and
not($testline =~ m/ecp5u/i) and
not($testline =~ m/ice40/i)) {
$line = '-- ' . $line;
}
}
# Comment "FOR xxxx : yyy USE ENTITY zzz;
if ($line =~ m/for\s+.+:.+\s+use\s+entity/i) {
$line = '-- ' . $line;
}
# Search for $Env_Var_Names and replace them by the value of the env_var
if ($testline =~ m/(\$[^\s\/.'"\\]+)/i) {
$envvar = $1;
$envvar =~ s/^.//;
eval {
$line =~ s/\$$envvar/$ENV{$envvar}/;
};
if ($@) {
print ("WARNING: Environment Variable not found: $envvar \n")
}
}
print tempFile ("$line\n");
}
close(tempFile);
close(HDLFile);
#-------------------------------------------------------------------------------
# delete original file and rename temporary file
#
unlink($hdlOutFileSpec);
rename($tempFileSpec, $hdlOutFileSpec);
if ($verbose == 1) {
print "$separator\n";
}
#if ($verbose == 1) {
# print $indent, "Hit any <CR> to continue";
# $dummy = <STDIN>;
#}

91
03-DigitalToAnalogConverter/Scripts/update_ise.pl Normal file
View File

@ -0,0 +1,91 @@
#!/usr/bin/perl
# ------------------------------------------------------------------------------
# update_ise
# replace ucf and vhd filelocation and name in the Xilinx xise project file
# Help Parameter : <?>
# Parameter : update_ise.pl <ISE File Spec> <VHDL File Spec> <UCF File Spec>
# ------------------------------------------------------------------------------
# Changelog:
# 2019-06-12 : zas
# * All parameters given with agruments instead of env variables
# 2015-05-26 : guo
# * update to environment from HELS v.15.0526
# 2012-05-27 : cof
# * Initial release
# ------------------------------------------------------------------------------
$separator = '-' x 79;
$indent = ' ' x 2;
$iseFileSpec = $ARGV[0];
$vhdlFileSpec = $ARGV[1];
$ucfFileSpec = $ARGV[2];
$verbose = 1;
if ($verbose == 1) {
print "Script Parameters:\n";
print " * iseFileSpec: $iseFileSpec\n";
print " * vhdlFileSpec: $vhdlFileSpec\n";
print " * ucfFileSpec: $ucfFileSpec\n";
}
#-------------------------------------------------------------------------------
# program I/O files
#
$tempFileSpec = $iseFileSpec . '.tmp';
if ($verbose == 1) {
print "\n$separator\n";
print "Updating file specifications in $iseFileSpec\n";
print $indent, "temporary file spec: $tempFileSpec\n";
}
#-------------------------------------------------------------------------------
# read original file, edit and save to temporary file
#
my $line;
open(ISEFile, $iseFileSpec) || die "couldn't open $iseFileSpec!";
open(tempFile, ">$tempFileSpec");
while (chop($line = <ISEFile>)) {
# replace VHDL files
if ($line =~ m/FILE_VHDL/i) {
$line =~ s/<file\s+xil_pn\:name=.*?".+?"/<file xil_pn:name="$vhdlFileSpec"/ig;
}
# replace EDIF files
if ($line =~ m/FILE_EDIF/i) {
$line =~ s/<file\s+xil_pn\:name=.*?".+?"/<file xil_pn:name="$edifFileSpec"/ig;
}
# replace UCF files
if ($line =~ m/FILE_UCF/i) {
$line =~ s/<file\s+xil_pn\:name=.*?".+?"/<file xil_pn:name="$ucfFileSpec"/ig;
}
# Implementation Top files
if ($line =~ m/\.vhd"/i) {
$line =~ s/<property\s+xil_pn:name="Implementation\s+Top\s+File"\s+xil_pn\:value=".+?"/<property xil_pn:name="Implementation Top File" xil_pn:value="$vhdlFileSpec"/ig;
}
if ($line =~ m/\.edf"/i) {
$line =~ s/<property\s+xil_pn:name="Implementation\s+Top\s+File"\s+xil_pn\:value=".+?"/<property xil_pn:name="Implementation Top File" xil_pn:value="$edifFileSpec"/ig;
}
# replace UCF binding
if ($line =~ m/\.ucf"/i) {
$line =~ s/<binding\s+(.+)\s+xil_pn\:name=.*?".+?"/<binding $1 xil_pn:name="$ucfFileSpec"/ig;
}
print tempFile ("$line\n");
}
close(tempFile);
close(ISEFile);
#-------------------------------------------------------------------------------
# delete original file and rename temporary file
#
unlink($iseFileSpec);
rename($tempFileSpec, $iseFileSpec);
if ($verbose == 1) {
print "$separator\n";
}

27
03-DigitalToAnalogConverter/Simulation/DAC.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /dac_tb/reset
add wave -noupdate /dac_tb/clock
add wave -noupdate -divider {parallel to serial}
add wave -noupdate -format Analog-Step -height 100 -max 66000.0 -radix unsigned /dac_tb/parallelIn
add wave -noupdate /dac_tb/serialOut
add wave -noupdate -divider {serial to parallel}
add wave -noupdate -format Analog-Step -height 100 -max 65500.000000000007 -radix unsigned /dac_tb/lowpassOut
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {88797414 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 175
configure wave -valuecolwidth 63
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits us
update
WaveRestoreZoom {0 ps} {105 us}

36
03-DigitalToAnalogConverter/Simulation/sineGen.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /sinegen_tb/reset
add wave -noupdate /sinegen_tb/clock
add wave -noupdate -format Analog-Step -height 30 -max 1300.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/phase
add wave -noupdate -divider {generator signals}
add wave -noupdate -format Analog-Step -height 40 -max 66000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/sawtooth
add wave -noupdate -format Analog-Step -height 40 -max 66000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/square
add wave -noupdate -format Analog-Step -height 40 -max 66000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/triangle
add wave -noupdate -divider sinewave
add wave -noupdate -format Analog-Step -height 80 -max 43200.0 -min -32800.0 -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/sineSamples
add wave -noupdate /sinegen_tb/I_DUT/newPolynom
add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/a
add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/b
add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/c
add wave -noupdate -radix decimal -radixshowbase 0 /sinegen_tb/I_DUT/d
add wave -noupdate -format Analog-Step -height 80 -max 76000.0 -radix unsigned -radixshowbase 0 /sinegen_tb/I_DUT/sine
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ns} 0}
quietly wave cursor active 0
configure wave -namecolwidth 250
configure wave -valuecolwidth 52
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1000
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits us
update
WaveRestoreZoom {0 ns} {52589 ns}
run 50 us

30
03-DigitalToAnalogConverter/Simulation/waveformGen.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /waveformgen_tb/reset
add wave -noupdate /waveformgen_tb/clock
add wave -noupdate /waveformgen_tb/en
add wave -noupdate -divider {generator signals}
add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/sawtooth
add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/square
add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/triangle
add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/polygon
add wave -noupdate -format Analog-Step -height 70 -max 66000.0 -radix unsigned -radixshowbase 0 /waveformgen_tb/I_DUT/sine
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ns} 0}
quietly wave cursor active 0
configure wave -namecolwidth 272
configure wave -valuecolwidth 89
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1000
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits us
update
WaveRestoreZoom {0 ns} {525 us}
run 500 us

32
03-DigitalToAnalogConverter/digitalToAnalogConverter.bash Executable file
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#!/bin/bash
#===============================================================================
# waveformGenerator.bash
# Starts HDL designer based on the generic hdlDesigner.bash
#
design_name=`basename $0 .bash`
design_directory=`dirname ${BASH_SOURCE[0]}`
hdl_script_name="$design_directory/Scripts/hdlDesigner.bash"
verbose=1
SEPARATOR='--------------------------------------------------------------------------------'
INDENT=' '
#-------------------------------------------------------------------------------
# Main script
#
if [ -n "$verbose" ] ; then
echo "$SEPARATOR"
echo "Launching HDL Designer"
echo "${INDENT}Design name is $design_name"
echo "${INDENT}Start directory is $design_directory"
echo "${INDENT}HDL designer script is $hdl_script_name"
fi
#-------------------------------------------------------------------------------
# Launch application
#
$hdl_script_name -v -d $design_directory -n $design_name -m hds.hdp

79
03-DigitalToAnalogConverter/digitalToAnalogConverter.bat Normal file
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::==============================================================================
:: eln_labs.bat
:: Starts HDL designer based on the generic hdlDesigner.bat
::
@echo off
::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
:: TO BE MODIFIED
::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
:: Define environment variables to be modified
:: You can change one or more values as needed
::
set VERBOSE=1
:: Define required Tools to be present
set REQUIRE_LIBS=0
set REQUIRE_HDS=1
set REQUIRE_MODELSIM=1
:: Set project name
set design_name=%~n0
:: Manually override Library & Tools Folder location
::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries
::set HDS_HOME=C:\eda\MentorGraphics\HDS
::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64
::set ISE_VERSION=14.7
::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE
::set LIBERO_HOME=C:\eda\Microsemi\Libero
::set SCRATCH_DIR=C:\temp\eda\%username%
::
::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
::------------------------------------------------------------------------------
:: Static environment variables
::
set SEPARATOR="--------------------------------------------------------------------------------"
set INDENT=" "
set design_directory=%~dp0
::remove trailing backslash
if %design_directory:~-1%==\ set design_directory=%design_directory:~0,-1%
pushd %design_directory%
set hdl_script_name="%design_directory:"=%\Scripts\hdlDesigner.bat"
::------------------------------------------------------------------------------
:: Main script
::
if %VERBOSE% == 1 (
echo "%SEPARATOR:"=%"
echo "-- HDL Designer Poject"
echo "%INDENT:"=%Design name is %design_name:"=%"
echo "%INDENT:"=%Start directory is %design_directory:"=%"
echo "%INDENT:"=%HDL designer script is %hdl_script_name:"=%"
echo.
)
::------------------------------------------------------------------------------
:: Launch application
::
if %VERBOSE% == 1 (
set command=%hdl_script_name% -v -n %design_name% -d %design_directory%
) else (
set command=%hdl_script_name% -n %design_name% -d %design_directory%
)
echo "Launch HDL Designer Script"
echo "%INDENT:"=%%command:"=%"
echo.
call %command%
:end
popd
echo.
echo -- %~nx0 Finished!
echo %SEPARATOR%
echo.
if not %errorlevel% lss 1 pause
goto:eof