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2024-02-23 13:01:05 +00:00
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6831
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/hds_user_prefs Normal file
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41
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/generate.tsk Normal file
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03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk Normal file
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version "1.1"
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03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk Normal file
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96
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk Normal file
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version "1.1"
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162
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk Normal file
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version "1.1"
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163
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk Normal file
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@ -0,0 +1,163 @@
version "1.1"
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13
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt Normal file
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FILE_NAMING_RULE: new_document.txt
DESCRIPTION_START
This is the default template used for the creation of Text Document files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
#
# Created:
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15
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd Normal file
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@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
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17
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd Normal file
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@ -0,0 +1,17 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
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-- VHDL Architecture %(library).%(unit).%(view)
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-- Created:
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%(entity)
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%(architecture)

19
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd Normal file
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@ -0,0 +1,19 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
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-- Created:
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CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
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END %(entity_name)_config;

15
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd Normal file
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@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Entity %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
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-- using Mentor Graphics HDL Designer(TM) %(version)
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%(entity)

16
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd Normal file
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@ -0,0 +1,16 @@
FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Body %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
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-- using Mentor Graphics HDL Designer(TM) %(version)
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PACKAGE BODY %(entity_name) IS
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18
03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd Normal file
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@ -0,0 +1,18 @@
FILE_NAMING_RULE: %(entity_name)_pkg.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Header files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Header %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE %(entity_name) IS
END %(entity_name);

6842
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/hds_user_prefs Normal file
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162
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk Normal file
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@ -0,0 +1,162 @@
version "1.1"
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bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp"
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41
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/generate.tsk Normal file
View File

@ -0,0 +1,41 @@
version "1.1"
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98
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk Normal file
View File

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"mapQuartusIPs"
"1"
"masterCov"
"0"
"peSe"
"EE"
"prevOnly"
"0"
"quartusSimDir"
"$HDS_PROJECT_DIR/QuartusIPSimLibs"
"replayScriptPath"
""
"saveReplayScript"
"0"
"server"
""
"showCmd"
"0"
"transcript"
"1"
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"0"
"useShortName"
"0"
"vhdlSwitches"
" -nologo"
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" -nologo"
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)
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onShortcutBar 1
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
)

83
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk Normal file
View File

@ -0,0 +1,83 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "ModelSim Flow"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp"
hasBitmap 1
tooltip "Generate and run entire ModelSim flow"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
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(preferedMap
preferedEnum 0
preferedSetting "$MODELSIM_HOME"
)
(preferedMap
preferedEnum 2
preferedSetting "ModelSim"
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onShortcutBar 1
onPulldownMenu 1
onToolbar 1
enabled 1
hierDepth 1
subTasks [
(HDSTaskRef
TaskName "Generate"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
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onShortcutBar 0
onPulldownMenu 0
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enabled 1
hierDepth 1
reffedTaskName "USER:Generate"
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(HDSTaskRef
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bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
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enabled 1
hierDepth 1
reffedTaskName "USER:ModelSim Compile"
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(HDSTaskRef
TaskName "ModelSim Simulate"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
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]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
reffedTaskName "USER:ModelSim Simulate"
)
]
)

98
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk Normal file
View File

@ -0,0 +1,98 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Simulate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp"
hasBitmap 1
tooltip "Invokes the ModelSim Simulator"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"1"
"runMethod"
"gui"
"runnableObject"
"ModelSimSimulator"
"runnableObjectType"
"tcl_plugin"
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"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"Arguments"
""
"Arguments1"
"do controller.do"
"Arguments2"
"controller.do"
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"1"
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"1"
"InitCmd"
"$SIMULATION_DIR/DAC.do"
"LogFile"
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""
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enabled 1
hierDepth 3
)

162
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk Normal file
View File

@ -0,0 +1,162 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Prepare for Synthesis"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp"
hasBitmap 1
tooltip "generates a single file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
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hierDepth 1
subTasks [
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associatedFileExt ""
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hasBitmap 1
tooltip "Performs generation of graphics files"
taskSettings [
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(SettingsMap
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""
"captureOutput"
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onShortcutBar 0
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(HDSTool
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associatedFileExt ""
TaskName "Concatenate HDL"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp"
hasBitmap 1
tooltip "Appends all HDL files together"
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""
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"%(concat_file)"
"outputVerilogFileExtension"
"v"
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"vhd"
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onPulldownMenu 0
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(HDSTool
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associatedFileExt ""
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bitmap "tool_default_tool.bmp"
hasBitmap 1
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hierDepth 3
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]
)

163
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk Normal file
View File

@ -0,0 +1,163 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Xilinx Project Navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp"
hasBitmap 1
tooltip "Xilinx Flow"
taskSettings [
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(SettingsMap
settingsMap [
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""
"taskInvocationScript"
""
]
)
]
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onShortcutBar 0
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hierDepth 1
subTasks [
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associatedFileExt ""
TaskName "Update.xise"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "Update file references in the Xilnx project .xise file"
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tooltip "Invokes the Xilinx ISE tool"
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For additional information, exceptions, compatibility issues and updates, visit SupportNet."
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"Xilinx XST"
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enabled 1
hierDepth 3
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)

13
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt Normal file
View File

@ -0,0 +1,13 @@
FILE_NAMING_RULE: new_document.txt
DESCRIPTION_START
This is the default template used for the creation of Text Document files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
#
# Created:
# by - %(user).%(group) (%(host))
# at - %(time) %(date)
#
# using Mentor Graphics HDL Designer(TM) %(version)
#

15
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(architecture)

17
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd Normal file
View File

@ -0,0 +1,17 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)
--
%(architecture)

19
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd Normal file
View File

@ -0,0 +1,19 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Configuration %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
END FOR;
END %(entity_name)_config;

15
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Entity %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)

16
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd Normal file
View File

@ -0,0 +1,16 @@
FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Body %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
PACKAGE BODY %(entity_name) IS
END %(entity_name);

18
03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd Normal file
View File

@ -0,0 +1,18 @@
FILE_NAMING_RULE: %(entity_name)_pkg.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Header files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Header %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE %(entity_name) IS
END %(entity_name);