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github-classroom[bot]
2024-02-23 13:01:05 +00:00
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06-07-08-09-SystemOnChip/AhbLiteComponents_test/doc/AMBA_AHB-Lite_spec.pdf Normal file
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06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbGpio_tester_test.vhd Normal file
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LIBRARY Common_test;
USE Common_test.testUtils.all;
ARCHITECTURE test OF ahbGpio_tester IS
-- reset and clock
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal clock_int: std_uLogic := '1';
signal reset_int: std_uLogic;
-- test information
signal noteTopSeparator : string(1 to 80) := (others => '-');
signal errorTopSeparator : string(1 to 80) := (others => '#');
signal bottomSeparator : string(1 to 80) := (others => '.');
signal indentation : string(1 to 2) := (others => ' ');
signal noteInformation : string(1 to 9) := (others => ' ');
signal errorInformation : string(1 to 10) := (others => ' ');
signal failureInformation : string(1 to 12) := (others => ' ');
signal testInformation : string(1 to 50) := (others => ' ');
-- register definition
constant peripheralBaseAddress: natural := 2**4;
constant dataRegisterAddress: natural := 0;
constant outputEnableRegisterAddress: natural := 1;
-- AMBA bus access
signal registerAddress: natural;
signal registerData: integer;
signal registerWrite: std_uLogic;
signal registerRead: std_uLogic;
signal writeFlag, readFlag, readFlag1: std_uLogic;
signal writeData, readData: integer;
-- GPIO access
signal ioData: integer;
signal ioMask: integer;
BEGIN
------------------------------------------------------------------------------
-- reset and clock
reset_int <= '1', '0' after 2*clockPeriod;
hReset_n <= not(reset_int);
clock_int <= not clock_int after clockPeriod/2;
hClk <= transport clock_int after clockPeriod*9.0/10.0;
------------------------------------------------------------------------------
-- test sequence
testSequence: process
begin
registerAddress <= 0;
registerData <= 0;
registerWrite <= '0';
registerRead <= '0';
ioData <= 0;
ioMask <= 0;
wait for 100 ns;
----------------------------------------------------------------------------
-- simple test
-- write en mask
testInformation <= pad("Writing data on the GPIO", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
ioData <= 16#AA#;
ioMask <= 16#0F#; wait for 0 ns;
registerAddress <= outputEnableRegisterAddress;
registerData <= ioMask;
registerWrite <= '1', '0' after clockPeriod/2;
wait for 4*clockPeriod;
-- write output data 55h
registerAddress <= dataRegisterAddress;
registerData <= 16#55#;
registerWrite <= '1', '0' after clockPeriod;
wait for 4*clockPeriod;
assert io = x"A5"
report
errorTopSeparator & cr &
noteInformation & indentation & "IO data not as expected" & cr &
noteInformation & bottomSeparator
severity error;
-- read data
testInformation <= pad("Reading data from the GPIO", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
registerAddress <= dataRegisterAddress;
registerRead <= '1', '0' after clockPeriod;
for index in 1 to 4 loop
wait until rising_edge(clock_int);
end loop;
assert readData = 16#A5#
report
errorTopSeparator & cr &
noteInformation & indentation & "read data not as expected" & cr &
noteInformation & bottomSeparator
severity error;
wait for 100 ns;
----------------------------------------------------------------------------
-- test with a different base address
-- write en mask
testInformation <= pad(
"Writing data to a different base address", testInformation'length
);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
ioData <= 16#AA#;
ioMask <= 16#F0#; wait for 0 ns;
registerAddress <= peripheralBaseAddress + outputEnableRegisterAddress;
registerData <= ioMask;
registerWrite <= '1', '0' after clockPeriod;
wait for 4*clockPeriod;
-- write output data 55h
registerAddress <= peripheralBaseAddress + dataRegisterAddress;
registerData <= 16#55#;
registerWrite <= '1', '0' after clockPeriod;
wait for 4*clockPeriod;
-- read data
registerAddress <= peripheralBaseAddress + dataRegisterAddress;
registerRead <= '1', '0' after clockPeriod;
for index in 1 to 4 loop
wait until rising_edge(clock_int);
end loop;
assert readData = 16#5A#
report
errorTopSeparator & cr &
noteInformation & indentation & "read data not as expected" & cr &
noteInformation & bottomSeparator
severity error;
wait for 4*clockPeriod;
----------------------------------------------------------------------------
-- access back to back
-- write en mask
testInformation <= pad("Accessing at full speed", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
wait until rising_edge(clock_int);
ioData <= 16#AA#;
ioMask <= 16#0F#; wait for 0 ns;
registerAddress <= outputEnableRegisterAddress;
registerData <= ioMask;
registerWrite <= '1' after clockPeriod/4, '0' after clockPeriod/2;
-- write output data 55h
wait until rising_edge(clock_int);
registerAddress <= dataRegisterAddress;
registerData <= 16#55#;
registerWrite <= '1' after clockPeriod/4, '0' after clockPeriod/2;
-- read data
wait until rising_edge(clock_int);
registerAddress <= dataRegisterAddress;
registerRead <= '1' after clockPeriod/4, '0' after clockPeriod/2;
for index in 1 to 4 loop
wait until rising_edge(clock_int);
end loop;
assert readData = 16#A5#
report
errorTopSeparator & cr &
noteInformation & indentation & "read data not as expected" & cr &
noteInformation & bottomSeparator
severity error;
wait for 4*clockPeriod;
-- end of simulation
wait for 100 ns;
testInformation <= pad("End of tests", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
failureInformation & indentation & testInformation & cr &
failureInformation & bottomSeparator
severity failure;
wait;
end process testSequence;
------------------------------------------------------------------------------
-- AMBA bus access
-- phase 1: address and controls
busAccess1: process
variable writeAccess: boolean := false;
begin
wait on reset_int, registerWrite, registerRead;
if falling_edge(reset_int) then
hAddr <= (others => '-');
hTrans <= transIdle;
hSel <= '0';
writeFlag <= '0';
end if;
if rising_edge(registerWrite) or rising_edge(registerRead) then
writeAccess := false;
if rising_edge(registerWrite) then
writeAccess := true;
end if;
wait until rising_edge(clock_int);
hAddr <= to_unsigned(registerAddress, hAddr'length),
(others => '-') after clockPeriod + 1 ns;
hTrans <= transNonSeq, transIdle after clockPeriod + 1 ns;
hSel <= '1', '0' after clockPeriod + 1 ns;
if writeAccess then
writeFlag <= '1', '0' after clockPeriod + 1 ns;
writeData <= registerData;
else
readFlag <= '1', '0' after clockPeriod + 1 ns;
end if;
end if;
end process busAccess1;
hWrite <= writeFlag;
-- phase 2: data write
busAccess2: process
begin
wait until rising_edge(clock_int);
hWData <= (others => '-');
readFlag1 <= '0';
if writeFlag = '1' then
hWData <= std_uLogic_vector(to_signed(writeData, hWData'length));
end if;
readFlag1 <= readFlag;
end process busAccess2;
-- phase 3: data read
busAccess3: process
begin
wait until rising_edge(clock_int);
if readFlag1 = '1' then
readData <= to_integer(to_01(unsigned(hRData)));
end if;
end process busAccess3;
------------------------------------------------------------------------------
-- GPIO access
linesAccess: process(ioData, ioMask)
variable ioDataVector: unsigned(io'range);
variable ioMaskVector: unsigned(io'range);
begin
ioDataVector := to_unsigned(ioData, ioDataVector'length);
ioMaskVector := to_unsigned(ioMask, ioMaskVector'length);
for index in io'range loop
if ioMaskVector(index) = '1' then
io(index) <= 'Z';
else
io(index) <= ioDataVector(index);
end if;
end loop;
end process;
END ARCHITECTURE test;

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06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbUart_tester_test.vhd Normal file
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LIBRARY Common_test;
USE Common_test.testUtils.all;
ARCHITECTURE test OF ahbUart_tester IS
-- reset and clock
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal clock_int: std_uLogic := '1';
signal reset_int: std_uLogic;
-- test information
signal noteTopSeparator : string(1 to 80) := (others => '-');
signal errorTopSeparator : string(1 to 80) := (others => '#');
signal bottomSeparator : string(1 to 80) := (others => '.');
signal indentation : string(1 to 2) := (others => ' ');
signal noteInformation : string(1 to 9) := (others => ' ');
signal errorInformation : string(1 to 10) := (others => ' ');
signal failureInformation : string(1 to 12) := (others => ' ');
signal testInformation : string(1 to 50) := (others => ' ');
-- register definition
constant dataRegisterAddress: natural := 0;
constant controlRegisterAddress: natural := 1;
constant scalerRegisterAddress: natural := 2;
constant statusRegisterAddress: natural := 1;
constant statusValidAddress: natural := 0;
constant valueRegisterAddress: natural := 1;
-- AMBA bus access
signal registerAddress: natural;
signal registerData: integer;
signal registerWrite: std_uLogic;
signal registerRead: std_uLogic;
signal writeFlag, readFlag, readFlag1: std_uLogic;
signal writeData, readData: integer;
-- UART access
constant baudPeriodNb: positive := 4;
signal uartData: integer;
signal uartSend: std_uLogic;
BEGIN
------------------------------------------------------------------------------
-- reset and clock
reset_int <= '1', '0' after 2*clockPeriod;
hReset_n <= not(reset_int);
clock_int <= not clock_int after clockPeriod/2;
hClk <= transport clock_int after clockPeriod*9.0/10.0;
------------------------------------------------------------------------------
-- test sequence
testSequence: process
begin
registerAddress <= 0;
registerData <= 0;
registerWrite <= '0';
registerRead <= '0';
uartSend <= '0';
wait for 1 us;
-- write baud rate
testInformation <= pad("Writing baud rate", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
registerAddress <= scalerRegisterAddress;
registerData <= baudPeriodNb;
registerWrite <= '1', '0' after clockPeriod;
wait for 4*clockPeriod;
-- write Tx data 55h
testInformation <= pad("Writing Tx data", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
registerAddress <= dataRegisterAddress;
registerData <= 16#55#;
registerWrite <= '1', '0' after clockPeriod;
wait for 20*baudPeriodNb*clockPeriod;
-- write Tx data 0Fh
testInformation <= (others => ' ');
wait for 1 ns;
testInformation <= pad("Writing Tx data", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
registerAddress <= dataRegisterAddress;
registerData <= 16#0F#;
registerWrite <= '1', '0' after clockPeriod;
wait for 4*clockPeriod;
-- read status
testInformation <= pad("Reading status", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
registerAddress <= statusRegisterAddress;
registerRead <= '1', '0' after clockPeriod;
for index in 1 to 4 loop
wait until rising_edge(clock_int);
end loop;
assert readData = 16#02#
report
errorTopSeparator & cr &
errorInformation & indentation &
"expected status sending flag" & cr &
errorInformation & bottomSeparator
severity error;
wait for 12*baudPeriodNb*clockPeriod;
-- read status
testInformation <= (others => ' ');
wait for 1 ns;
testInformation <= pad("Reading status", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
registerRead <= '1', '0' after clockPeriod;
for index in 1 to 4 loop
wait until rising_edge(clock_int);
end loop;
assert readData = 16#00#
report
errorTopSeparator & cr &
errorInformation & indentation &
"expected no flag" & cr &
errorInformation & bottomSeparator
severity error;
wait for 20*baudPeriodNb*clockPeriod;
-- receive AAh
testInformation <= pad("Receiving Rx data", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
uartData <= 16#AA#;
uartSend <= '1', '0' after clockPeriod;
wait for 4*clockPeriod;
-- read status
testInformation <= pad("Reading status", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
registerAddress <= statusRegisterAddress;
registerRead <= '1', '0' after clockPeriod;
for index in 1 to 4 loop
wait until rising_edge(clock_int);
end loop;
assert readData = 16#04#
report
errorTopSeparator & cr &
errorInformation & indentation &
"expected status receiving flag" & cr &
errorInformation & bottomSeparator
severity error;
wait for 10*baudPeriodNb*clockPeriod;
-- read status again
testInformation <= (others => ' ');
wait for 1 ns;
testInformation <= pad("Reading status", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
registerRead <= '1', '0' after clockPeriod;
for index in 1 to 4 loop
wait until rising_edge(clock_int);
end loop;
assert readData = 16#01#
report
errorTopSeparator & cr &
errorInformation & indentation &
"expected status data available flag" & cr &
errorInformation & bottomSeparator
severity error;
wait for 4*clockPeriod;
-- read data
testInformation <= pad("Reading data", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
registerAddress <= dataRegisterAddress;
registerRead <= '1', '0' after clockPeriod;
for index in 1 to 4 loop
wait until rising_edge(clock_int);
end loop;
assert readData = 16#AA#
report
errorTopSeparator & cr &
errorInformation & indentation & "read data not as expected" & cr &
errorInformation & bottomSeparator
severity error;
wait for 4*clockPeriod;
-- read status
testInformation <= pad("Reading status", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
noteInformation & indentation & testInformation & cr &
noteInformation & bottomSeparator
severity note;
registerAddress <= statusRegisterAddress;
registerRead <= '1', '0' after clockPeriod;
for index in 1 to 4 loop
wait until rising_edge(clock_int);
end loop;
assert readData = 16#00#
report
errorTopSeparator & cr &
errorInformation & indentation &
"expected no flag" & cr &
errorInformation & bottomSeparator
severity error;
wait for 4*clockPeriod;
-- end of simulation
wait for 100 ns;
testInformation <= pad("End of tests", testInformation'length);
wait for 0 ns;
assert false
report
noteTopSeparator & cr &
failureInformation & indentation & testInformation & cr &
failureInformation & bottomSeparator
severity failure;
wait;
end process testSequence;
------------------------------------------------------------------------------
-- AMBA bus access
-- phase 1: address and controls
busAccess1: process
variable writeAccess: boolean := false;
begin
wait on reset_int, registerWrite, registerRead;
if falling_edge(reset_int) then
hAddr <= (others => '-');
hTrans <= transIdle;
hSel <= '0';
writeFlag <= '0';
end if;
if rising_edge(registerWrite) or rising_edge(registerRead) then
writeAccess := false;
if rising_edge(registerWrite) then
writeAccess := true;
end if;
wait until rising_edge(clock_int);
hAddr <= to_unsigned(registerAddress, hAddr'length),
(others => '-') after clockPeriod + 1 ns;
hTrans <= transNonSeq, transIdle after clockPeriod + 1 ns;
hSel <= '1', '0' after clockPeriod + 1 ns;
if writeAccess then
writeFlag <= '1', '0' after clockPeriod + 1 ns;
writeData <= registerData;
else
readFlag <= '1', '0' after clockPeriod + 1 ns;
end if;
end if;
end process busAccess1;
hWrite <= writeFlag;
-- phase 2: data write
busAccess2: process
begin
wait until rising_edge(clock_int);
hWData <= (others => '-');
readFlag1 <= '0';
if writeFlag = '1' then
hWData <= std_uLogic_vector(to_signed(writeData, hWData'length));
end if;
readFlag1 <= readFlag;
end process busAccess2;
-- phase 3: data read
busAccess3: process
begin
wait until rising_edge(clock_int);
if readFlag1 = '1' then
readData <= to_integer(to_01(unsigned(hRData)));
end if;
end process busAccess3;
------------------------------------------------------------------------------
-- UART access
sendByte: process
variable serialData: unsigned(7 downto 0);
begin
-- send stop bit
RxD <= '1';
-- get new word
wait until rising_edge(uartSend);
serialData := to_unsigned(uartData, serialData'length);
-- send start bit
RxD <= '0';
wait for baudPeriodNb * clockPeriod;
-- send data bits
for index in serialData'reverse_range loop
RxD <= serialData(index);
wait for baudPeriodNb * clockPeriod;
end loop;
end process sendByte;
END ARCHITECTURE test;

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06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/uvmAhbDriver_sim.vhd Normal file
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LIBRARY std;
USE std.TEXTIO.all;
LIBRARY Common_test;
USE Common_test.testUtils.all;
ARCHITECTURE RTL OF uvmAhbDriver IS
constant flipflopDelay: time := 1 ns;
signal hAddr1, hWData1, hWData2: natural := 0;
signal hWrite1, hWrite2, hRead1, hRead2: std_ulogic := '0';
BEGIN
------------------------------------------------------------------------------
-- reset and clock
hReset_n <= not(reset);
hClk <= clock;
------------------------------------------------------------------------------
-- interpret transaction
interpretTransaction: process(driverTransaction)
variable my_line : line;
variable command_part : line;
begin
write(my_line, driverTransaction);
read_first(my_line, command_part);
if command_part.all = "write" then
read_first(my_line, command_part);
hAddr1 <= sscanf(command_part.all);
read_first(my_line, command_part);
hWData1 <= sscanf(command_part.all);
hWrite1 <= '1', '0' after 1 ns;
elsif command_part.all = "read" then
read_first(my_line, command_part);
hAddr1 <= sscanf(command_part.all);
hRead1 <= '1', '0' after 1 ns;
end if;
deallocate(my_line);
end process interpretTransaction;
-- expand pulses to the next clock
expandReadWrite: process
begin
hRead2 <= '0';
hWrite2 <= '0';
wait on hRead1, hWrite1;
hRead2 <= hRead1;
hWrite2 <= hWrite1;
wait until rising_edge(clock);
end process expandReadWrite;
-- delay signals 1 or 2 clock periods
synchAccess: process(reset, clock)
begin
if reset = '1' then
hAddr <= (others => '0');
hWData2 <= 0;
hWData <= (others => '0');
hWrite <= '0';
hSel <= '0';
hTrans <= transIdle;
elsif rising_edge(clock) then
hAddr <= to_unsigned(hAddr1, hAddr'length) after flipflopDelay;
hWData2 <= hWData1;
hWData <= std_ulogic_vector(to_unsigned(hWData2, hWData'length)) after flipflopDelay;
hWrite <= hWrite2 after flipflopDelay;
hSel <= hWrite2 or hRead2 after flipflopDelay;
if (hWrite2 = '1') or (hRead2 = '1') then
hTrans <= transNonSeq after flipflopDelay;
else
hTrans <= transIdle after flipflopDelay;
end if;
end if;
end process synchAccess;
END ARCHITECTURE RTL;

49
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LIBRARY Common_test;
USE Common_test.testUtils.all;
ARCHITECTURE RTL OF uvmAhbMonitor IS
signal addressReg: unsigned(hAddr'range);
signal writeReg: std_ulogic;
signal readReg: std_ulogic;
BEGIN
------------------------------------------------------------------------------
-- register address and controls
storeControls: process(hReset_n, hClk)
begin
if not(hReset_n) = '1' then
addressReg <= (others => '0');
writeReg <= '0';
readReg <= '0';
elsif rising_edge(hClk) then
writeReg <= '0';
readReg <= '0';
if (hSel = '1') and (hTrans = transNonSeq) then
addressReg <= hAddr(addressReg'range);
writeReg <= hWrite;
readReg <= not hWrite;
end if;
end if;
end process storeControls;
-- monitor acesses
reportBusAccess: process(hReset_n, hClk)
begin
if not(hReset_n) = '1' then
monitorTransaction <= pad( false, ' ', monitorTransaction'length, "idle");
elsif rising_edge(hClk) then
if readReg = '1' then
monitorTransaction <= pad(
false, ' ', monitorTransaction'length,
"read " & sprintf("%04X", addressReg) & ' ' & sprintf("%04X", hRData)
);
elsif writeReg = '1' then
monitorTransaction <= pad(
false, ' ', monitorTransaction'length,
"written " & sprintf("%04X", addressReg) & ' ' & sprintf("%04X", hWData)
);
end if;
end if;
end process reportBusAccess;
END ARCHITECTURE RTL;

1
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbGpio_tester_test.vhd._fpf Normal file
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DIALECT atom VHDL_2008

1
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbUart_tester_test.vhd._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_entity.vhg._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_ANY

1
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_struct.vhg._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_ANY

1
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tester_entity.vhg._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_ANY

1
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbuart_tb_entity.vhg._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbuart_tb_struct.vhg._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbuart_tester_entity.vhg._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_ANY

1
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_uvmAhbDriver_sim.vhd._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_uvmAhbMonitor_sim.vhd._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

3
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbgpio_tb._epf Normal file
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@ -0,0 +1,3 @@
DEFAULT_FILE atom ahb@gpio_tb/struct.bd
DEFAULT_ARCHITECTURE atom struct
TOP_MARKER atom 1

2
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbgpio_tester._epf Normal file
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@ -0,0 +1,2 @@
DEFAULT_ARCHITECTURE atom test
DEFAULT_FILE atom ahbGpio_tester_test.vhd

3
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbuart_tb._epf Normal file
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@ -0,0 +1,3 @@
DEFAULT_FILE atom ahb@uart_tb/struct.bd
DEFAULT_ARCHITECTURE atom struct
TOP_MARKER atom 1

2
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbuart_tester._epf Normal file
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DEFAULT_ARCHITECTURE atom test
DEFAULT_FILE atom ahbUart_tester_test.vhd

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DEFAULT_FILE atom uvm@ahb@agent@hw/struct.bd
DEFAULT_ARCHITECTURE atom struct

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DEFAULT_FILE atom uvmAhbDriver_sim.vhd
DEFAULT_ARCHITECTURE atom RTL

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DEFAULT_FILE atom uvmAhbMonitor_sim.vhd
DEFAULT_ARCHITECTURE atom RTL

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