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2024-02-23 13:01:05 +00:00
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commit d212040c30
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40
Libs/RiscV/HEIRV32/hdl/ALU_rtl.vhd Normal file
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-- Risc-V ed. 2022 page 250 (pdf page 273)
ARCHITECTURE rtl OF ALU IS
signal lvec_res : std_ulogic_vector(res'range);
signal lsig_zero : std_ulogic;
BEGIN
lsig_zero <= '1' when lvec_res = (lvec_res'range => '0') else '0';
zero <= lsig_zero after g_tALU;
res <= lvec_res after g_tALU;
alu : process(srcA, srcB, ctrl)
begin
case ctrl is
when "000" => -- add
lvec_res <= std_ulogic_vector(resize(
unsigned(srcA) + unsigned(srcB), lvec_res'length
));
when "001" => -- substract
lvec_res <= std_ulogic_vector(resize(
unsigned(srcA) - unsigned(srcB), lvec_res'length
));
when "010" => -- AND
lvec_res <= srcA and srcB;
when "011" => -- OR
lvec_res <= srcA or srcB;
when "101" => -- SLT
if srcA < srcB then
lvec_res <= (lvec_res'high downto 1 => '0') & '1';
else
lvec_res <= (lvec_res'high downto 1 => '0') & '0';
end if;
when others => -- unknown
lvec_res <= (others => '-');
end case;
end process alu;
END ARCHITECTURE rtl;

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Libs/RiscV/HEIRV32/hdl/aluDecoder_rtl.vhd Normal file
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ARCHITECTURE rtl OF aluDecoder IS
signal lsig_rTypeSub : std_ulogic;
BEGIN
lsig_rTypeSub <= funct7 and op; -- true for R-type substract
decode : process(op, funct3, funct7, ALUOp, lsig_rTypeSub)
begin
case ALUOp is
when "00" => ALUControl <= "000" after g_tDec; -- addition
when "01" => ALUControl <= "001" after g_tDec; -- substraction
when others =>
case funct3 is -- R-type or I-type
when "000" =>
if lsig_rTypeSub = '1' then
ALUControl <= "001" after g_tDec; -- sub
else
ALUControl <= "000" after g_tDec; -- add, addi
end if;
when "010" => ALUControl <= "101" after g_tDec; -- slt, slti
when "110" => ALUControl <= "011" after g_tDec; -- or, ori
when "111" => ALUControl <= "010" after g_tDec; -- and, andi
when others => ALUControl <= "---" after g_tDec; -- unknown
end case;
end case;
end process decode;
END ARCHITECTURE rtl;

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Libs/RiscV/HEIRV32/hdl/bramAddrReducer_rtl.vhd Normal file
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ARCHITECTURE rtl OF bramAddrReducer IS
BEGIN
-- +2 to srr(2) the address (as it makes +4)
addrOut <= std_ulogic_vector(addrIn(addrOut'high+2 downto addrOut'low+2));
END ARCHITECTURE rtl;

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Libs/RiscV/HEIRV32/hdl/bufferStdULogEnable_rtl.vhd Normal file
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ARCHITECTURE rtl OF bufferStdULogEnable IS
BEGIN
buffering:process(rst, CLK)
begin
if rst = '1' then
out1 <= (others=>'0');
elsif rising_edge(CLK) then
if EN = '1' then
out1 <= in1;
end if;
end if;
end process buffering;
END ARCHITECTURE rtl;

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Libs/RiscV/HEIRV32/hdl/bufferUnsignedEnable_rtl.vhd Normal file
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ARCHITECTURE rtl OF bufferUnsignedEnable IS
BEGIN
buffering:process(rst, CLK)
begin
if rst = '1' then
out1 <= (others=>'0') after g_tPC;
elsif rising_edge(CLK) then
if EN = '1' then
out1 <= in1 after g_tPC;
end if;
end if;
end process buffering;
END ARCHITECTURE rtl;

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Libs/RiscV/HEIRV32/hdl/extend_rtl.vhd Normal file
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ARCHITECTURE rtl OF extend IS
BEGIN
extend : process(input, src)
begin
case src is
when "00" => -- I-type
extended <= (12 to 31 => input(31)) &
input(31 downto 20) after g_tExt;
when "01" => -- S-types (stores)
extended <= (12 to 31 => input(31)) &
input(31 downto 25) & input(11 downto 7) after g_tExt;
when "10" => -- B-type (branches)
extended <= (12 to 31 => input(31)) & input(7) &
input(30 downto 25) & input(11 downto 8) & '0' after g_tExt;
when "11" => -- J-type (jal)
extended <= (20 to 31 => input(31)) &
input(19 downto 12) & input(20) &
input(30 downto 21) & '0' after g_tExt;
when others => -- impossible
extended <= (others => '-') after g_tExt;
end case;
end process extend;
END ARCHITECTURE rtl;

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Libs/RiscV/HEIRV32/hdl/mux4To1ULogVec_rtl.vhd Normal file
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ARCHITECTURE rtl OF mux4To1ULogVec IS
BEGIN
muxSelect: process(sel, in1, in2, in3, in4)
begin
case to_integer(unsigned(sel)) is
when 0 => out1 <= in1 after g_tMux;
when 1 => out1 <= in2 after g_tMux;
when 2 => out1 <= in3 after g_tMux;
when 3 => out1 <= in4 after g_tMux;
when others => out1 <= (others => 'X') after g_tMux;
end case;
end process muxSelect;
END ARCHITECTURE rtl;

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Libs/RiscV/HEIRV32/hdl/registerFile_rtl.vhd Normal file
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ARCHITECTURE rtl OF registerFile IS
-- Bank of register
type t_registersBank is array (31 downto 0) of
std_ulogic_vector(31 downto 0);
-- A bank of registers
signal larr_registers: t_registersBank;
signal lvec_btns : std_ulogic_vector(31 downto 0);
BEGIN
-- Special regs
process(rst, clk)
begin
if rst = '1' then
lvec_btns <= (others => '0');
elsif rising_edge(clk) then
lvec_btns <= (btns'length to g_datawidth-1 => '0') & btns;
end if;
end process;
-- Clocked write
process(rst, clk) begin
if rst = '1' then
larr_registers <= (others => (others => '0')) after g_tRfWr;
elsif rising_edge(clk) then
if writeEnable3 = '1' and en = '1' then
larr_registers(to_integer(unsigned(addr3))) <= writeData after (g_tRfWr + g_tSetup);
end if;
end if;
end process;
-- Comb. read
-- Addr 0 wired to 0s
process(addr1, addr2) begin
if (to_integer(unsigned(addr1)) = 0) then
RD1 <= (others => '0') after g_tRfRd;
elsif (to_integer(unsigned(addr1)) = 31) then -- buttons
RD1 <= lvec_btns after g_tRfRd;
else
RD1 <= larr_registers(to_integer(unsigned(addr1))) after g_tRfRd;
end if;
if (to_integer(unsigned(addr2)) = 0) then
RD2 <= (others => '0') after g_tRfRd;
elsif (to_integer(unsigned(addr2)) = 31) then -- buttons
RD2 <= lvec_btns after g_tRfRd;
else
RD2 <= larr_registers(to_integer(unsigned(addr2))) after g_tRfRd;
end if;
end process;
leds <= larr_registers(30);
END ARCHITECTURE rtl;