1
0

implement math approch for interpolation

This commit is contained in:
Rémi Heredero 2024-03-12 11:59:10 +01:00
parent e187e34017
commit f086447f28
7 changed files with 45 additions and 16 deletions

View File

@ -1280,8 +1280,8 @@ projectPaths [
"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp" "C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\work\\edu\\sem\\labo\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp" "C:\\work\\edu\\sem\\labo\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\hds.hdp" "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\Users\\uadmin\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp" "C:\\Users\\uadmin\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
] ]
libMappingsRootDir "" libMappingsRootDir ""
teamLibMappingsRootDir "" teamLibMappingsRootDir ""

View File

@ -1281,6 +1281,7 @@ projectPaths [
"C:\\work\\edu\\sem\\labo\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp" "C:\\work\\edu\\sem\\labo\\sem_labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\hds.hdp" "C:\\dev\\sem-labs\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp" "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
"C:\\Users\\uadmin\\GIT\\2024-sem-labs-herederoremi\\02-SplineInterpolator\\Prefs\\hds.hdp"
] ]
libMappingsRootDir "" libMappingsRootDir ""
teamLibMappingsRootDir "" teamLibMappingsRootDir ""
@ -4149,7 +4150,7 @@ hdsWorkspaceLocation ""
relativeLibraryRootDir "" relativeLibraryRootDir ""
vmLabelLatestDontAskAgain 0 vmLabelLatestDontAskAgain 0
vmLabelWorkspaceDontAskAgain 0 vmLabelWorkspaceDontAskAgain 0
logWindowGeometry "600x573+405+95" logWindowGeometry "600x573+406+95"
diagramBrowserTabNo 0 diagramBrowserTabNo 0
showInsertPortHint 0 showInsertPortHint 0
showContentFirstTime 0 showContentFirstTime 0
@ -6217,9 +6218,9 @@ size 180
] ]
displayHierarchy 0 displayHierarchy 0
xPos 0 xPos 0
yPos 14 yPos 4
width 1936 width 892
height 1056 height 982
activeSidePanelTab 2 activeSidePanelTab 2
activeLibraryTab 2 activeLibraryTab 2
sidePanelSize 278 sidePanelSize 278

View File

@ -1,20 +1,54 @@
ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS
subtype sample_type is signed(sampleIn'range); subtype sample_type is signed(coeffBitNb-1+oversamplingBitNb DOWNTO 0);
type samples_type is array (1 to 4) of sample_type; type order0 is array (0 to 0) of sample_type;
signal samples: samples_type; type order1 is array (0 to 1) of sample_type;
type order2 is array (0 to 2) of sample_type;
type order3 is array (0 to 3) of sample_type;
signal cA: order3;
signal cB: order2;
signal cC: order1;
signal cD: order0;
BEGIN BEGIN
process(clock, reset) begin process(clock, reset) begin
if reset = '1' then if reset = '1' then
samples <= (others => (others => '0')); cA <= (others => (others => '0'));
cB <= (others => (others => '0'));
cC <= (others => (others => '0'));
cD <= (others => (others => '0'));
elsif rising_edge(clock) then elsif rising_edge(clock) then
if restartPolynom = '1' then
cA(3) <= (others => '0');
cA(2) <= (others => '0');
cA(1) <= (others => '0');
cA(0) <= resize(a,sample_type'high+1);
cB(2) <= (others => '0');
cB(1) <= (others => '0');
cB(0) <= resize(b,sample_type'high+1);
cC(1) <= (others => '0');
cC(0) <= resize(c,sample_type'high+1);
cD(0) <= resize(d,sample_type'high+1);
else
cC(1) <= resize(c,sample_type'high+1) + cC(1);
cB(2) <= cB(2) + resize(2*cB(1),sample_type'high+1) + b;
cB(1) <= resize(b,sample_type'high+1) + cB(1);
cA(3) <= cA(3) + resize(3*cA(2),sample_type'high+1) + resize(3*cA(1),sample_type'high+1) + a;
cA(2) <= cA(2) + resize(2*cA(1),sample_type'high+1) + a;
cA(1) <= resize(A,sample_type'high+1) + cA(1);
end if;
end if; end if;
end process; end process;
sampleOut <= (others => '0'); sampleOut <= resize(cA(3)+cB(2)+cC(1)+cD(0),signalBitNb);
END ARCHITECTURE studentVersion; END ARCHITECTURE studentVersion;

View File

@ -1,6 +0,0 @@
EDIT_LOCK
remi.heredero
UNKNOWN
WE2330808
17492
08.03.2024-12:51:15.116000