forked from HEL/circuiteria
feat: add ports on group elements
Groups now accept ports/ports-margins like blocks. Port name labels default to outside the group border (outside-port-names: true) so they don't overlap child elements; set to false for block-style inside labels.
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// Demonstrates ports on a group element.
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// outside-port-names: true (default) — labels outside the group border
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// outside-port-names: false — labels inside (block-style)
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#import "/src/lib.typ": circuit, element, util, wire
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#set page(width: auto, height: auto, margin: .5cm)
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#circuit({
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// --- Group with port labels OUTSIDE (default) ---
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element.group(
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id: "cpu",
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name: "CPU (labels outside)",
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name-anchor: "north",
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stroke: (dash: "dashed"),
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fill: util.colors.yellow.lighten(60%),
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padding: 1em,
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outside-port-names: true,
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ports: (
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west: (
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(id: "in1", name: "D1"),
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(id: "in2", name: "D2"),
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),
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east: ((id: "out", name: "Q"),),
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south: (
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(id: "rst", name: "RST", vertical: true),
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(id: "done", name: "DONE", vertical: true),
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),
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),
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{
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element.block(
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id: "reg2",
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w: 2.5,
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h: 3,
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x: 0,
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y: 0,
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fill: util.colors.green,
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ports: (
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west: ((id: "d1"), (id: "d2")),
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east: ((id: "q"),),
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north: ((id: "clk", clock: true),),
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),
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)
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},
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)
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// --- Group with port labels INSIDE (outside-port-names: false) ---
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element.group(
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id: "cpu2",
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name: "CPU (labels inside)",
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name-anchor: "north",
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stroke: (dash: "dashed"),
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fill: util.colors.yellow.lighten(60%),
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padding: 4em,
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outside-port-names: false,
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ports: (
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west: (
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(id: "in1", name: "D1"),
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(id: "in2", name: "D2"),
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),
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east: ((id: "out", name: "Q"),),
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south: (
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(id: "rst", name: "RST", vertical: true),
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(id: "done", name: "DONE", vertical: true),
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),
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),
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{
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element.block(
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id: "reg2",
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w: 2.5,
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h: 3,
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x: 10,
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y: 0,
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fill: util.colors.green,
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ports: (
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west: ((id: "d1"), (id: "d2")),
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east: ((id: "q"),),
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north: ((id: "clk", clock: true),),
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),
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)
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},
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)
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wire.stub("cpu2-port-in1", "west", name: "A")
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wire.stub("cpu2-port-in2", "west", name: "B")
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wire.stub("cpu2-port-out", "east", name: "Q")
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})
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