added riscv examples

gallery/riscv/mem_instr.yaml

@@ -0,0 +1,78 @@
+structures:
+  main:
+    bits: 32
+    ranges:
+      31-20:
+        name: src
+        depends-on: 5
+        values:
+          0:
+            description:
+            structure: srcImmediate
+          1:
+            description:
+            structure: srcRegister
+      19-15:
+        name: rs1
+      14-12:
+        name: funct3
+        description: function modifier
+        values:
+          000: byte
+          001: half-word
+          "010": word
+          100: upper byte (load only)
+          101: upper half (load only)
+      11-7:
+        name: dst
+        depends-on: 5
+        values:
+          0:
+            description:
+            structure: dstRegister
+          1:
+            description:
+            structure: dstImmediate
+      6:
+        name: 0
+      5:
+        name: I
+      4:
+        name: 0
+      3:
+        name: 0
+      2:
+        name: 0
+      1:
+        name: 1
+      0:
+        name: 1
+
+  srcImmediate:
+    bits: 12
+    ranges:
+      11-0:
+        name: src
+        description: source memory address
+  srcRegister:
+    bits: 12
+    ranges:
+      11-5:
+        name: dstU
+        description: destination address upper bits
+      4-0:
+        name: rs2
+        description: source register
+
+  dstImmediate:
+    bits: 5
+    ranges:
+      4-0:
+        name: destL
+        description: destination address lower bits
+  dstRegister:
+    bits: 5
+    ranges:
+      4-0:
+        name: rd
+        description: destination register