23 Commits

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Author	SHA1	Message	Date
LordBaryhobal	7731159dd0	added h-ratio to MUX + fixed inputs spacing	2024-05-18 16:50:14 +02:00
LordBaryhobal	699b3c0189	added name anchor to ALU	2024-05-18 16:48:25 +02:00
LordBaryhobal	08f931bbde	added small clock ports	2024-05-18 16:46:32 +02:00
LordBaryhobal	7da2bb2b64	fixed extender ports + added align-out param	2024-05-18 16:46:18 +02:00
LordBaryhobal	e4194d0925	added horizontal zigzag wires	2024-05-18 16:45:09 +02:00
LordBaryhobal	86d9122740	added groups	2024-05-18 13:06:57 +02:00
LordBaryhobal	5bd3dd8111	added more customization options for wires	2024-05-18 12:39:47 +02:00
LordBaryhobal	66ac91af7b	added stub name offset parameter	2024-05-17 23:52:43 +02:00
LordBaryhobal	047c3b8893	improved doc + made it fancier	2024-05-17 23:07:17 +02:00
LordBaryhobal	64a6146f32	added doc for gates + minor changes	2024-05-17 22:24:38 +02:00
LordBaryhobal	8ec245f36e	added logic gates	2024-05-17 21:19:40 +02:00
LordBaryhobal	a9014e03e9	added doc cross-reference links	2024-05-17 18:12:25 +02:00
LordBaryhobal	c01e33cab4	added blue color	2024-05-17 16:58:40 +02:00
LordBaryhobal	9e4767663e	removed main.typ	2024-05-17 16:53:35 +02:00
LordBaryhobal	4d97062d30	improved doc + moved examples to separate file	2024-05-17 16:52:43 +02:00
LordBaryhobal	ccc38c3e1d	added doc for elements	2024-05-17 14:19:27 +02:00
LordBaryhobal	21b5d1cbfe	fixed multiplexers with named ports + minor changes	2024-05-17 14:18:33 +02:00
LordBaryhobal	7e0209b712	added doc for circuit, util and wire	2024-05-17 09:36:38 +02:00
LordBaryhobal	ef4461bd18	added relative x coordinates	2024-05-17 00:11:04 +02:00
LordBaryhobal	6174baf650	added test diagram	2024-05-16 23:35:54 +02:00
LordBaryhobal	6d6c357534	split up sources into manageable files	2024-05-16 23:35:53 +02:00
LordBaryhobal	c9155a0b99	initial commit	2024-05-16 23:35:53 +02:00
Louis Heredero	1e6c6cfc43	Initial commit	2024-05-16 21:34:50 +00:00