forked from HEL/circuiteria
purpl3F0x
0c1272e35e
- Introduced `verilog.typ` for parsing Verilog/SystemVerilog source code, supporting both ANSI and non-ANSI port styles. - Implemented functions to analyze modules, infer AXI4, AXI4-Lite, and AXI4-Stream buses, as well as clock and reset signals. - Added rendering capabilities for Verilog modules, allowing for visual representation of ports and buses. - Created a new `gallery/verilog.typ` file to facilitate the drawing of Verilog blocks in diagrams. Signed-off-by: Stavros Avramidis <stavros9899@gmail.com>
