forked from HEL/circuiteria
purpl3F0x
0c1272e35e
- Introduced `verilog.typ` for parsing Verilog/SystemVerilog source code, supporting both ANSI and non-ANSI port styles. - Implemented functions to analyze modules, infer AXI4, AXI4-Lite, and AXI4-Stream buses, as well as clock and reset signals. - Added rendering capabilities for Verilog modules, allowing for visual representation of ports and buses. - Created a new `gallery/verilog.typ` file to facilitate the drawing of Verilog blocks in diagrams. Signed-off-by: Stavros Avramidis <stavros9899@gmail.com>
2.4 KiB
2.4 KiB
circuiteria
Circuiteria is a Typst package for drawing block circuit diagrams using the CeTZ package.
Examples
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| A bit of everything | |
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| Wires everywhere | |
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| Groups | Rotated |
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| Generated from a Verilog module | |
Note
These circuit layouts were copied from a digital design course given by prof. S. Zahno and recreated using this package
Click on the example image to jump to the code.
Usage
For more information, see the manual
To use this package, simply import circuiteria and call the circuit function:
#import "@preview/circuiteria:0.2.1"
#circuiteria.circuit({
import circuiteria: *
...
})
Verilog modules
Blocks can be generated automatically from Verilog/SystemVerilog sources. AXI4, AXI4-Lite and AXI4-Stream signals are grouped into single bus ports, and clock/reset signals are detected and placed together:
#circuiteria.circuit({
import circuiteria: *
verilog.block(read("my_module.v"), x: 0, y: 0)
})
The port ids are the signal names, or the bus prefixes for inferred buses
(e.g. "my_module-port-s_axi").