forked from HEL/circuiteria
purpl3F0x
0c1272e35e
- Introduced `verilog.typ` for parsing Verilog/SystemVerilog source code, supporting both ANSI and non-ANSI port styles. - Implemented functions to analyze modules, infer AXI4, AXI4-Lite, and AXI4-Stream buses, as well as clock and reset signals. - Added rendering capabilities for Verilog modules, allowing for visual representation of ports and buses. - Created a new `gallery/verilog.typ` file to facilitate the drawing of Verilog blocks in diagrams. Signed-off-by: Stavros Avramidis <stavros9899@gmail.com>
52 lines
2.0 KiB
Verilog
52 lines
2.0 KiB
Verilog
`timescale 1ns / 1ps
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// Simple AXI-Stream to AXI4-Lite bridge used as a demo for the Verilog parser
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module axi_demo #(
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parameter integer DATA_WIDTH = 32,
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parameter integer ADDR_WIDTH = 12
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) (
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input wire aclk,
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input wire aresetn,
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// AXI4-Lite slave interface
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input wire [ADDR_WIDTH-1:0] s_axil_awaddr,
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input wire [2:0] s_axil_awprot,
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input wire s_axil_awvalid,
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output wire s_axil_awready,
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input wire [31:0] s_axil_wdata,
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input wire [3:0] s_axil_wstrb,
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input wire s_axil_wvalid,
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output wire s_axil_wready,
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output wire [1:0] s_axil_bresp,
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output wire s_axil_bvalid,
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input wire s_axil_bready,
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input wire [ADDR_WIDTH-1:0] s_axil_araddr,
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input wire [2:0] s_axil_arprot,
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input wire s_axil_arvalid,
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output wire s_axil_arready,
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output wire [31:0] s_axil_rdata,
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output wire [1:0] s_axil_rresp,
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output wire s_axil_rvalid,
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input wire s_axil_rready,
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// AXI4-Stream sink
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input wire [63:0] s_axis_tdata,
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input wire [7:0] s_axis_tkeep,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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// AXI4-Stream source
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output wire [63:0] m_axis_tdata,
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output wire [7:0] m_axis_tkeep,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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input wire enable,
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output wire [3:0] status,
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output wire irq
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);
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endmodule
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