circuiteria/README.md

circuiteria

Circuiteria is a Typst package for drawing block circuit diagrams using the CeTZ package.

Examples

A bit of everything
Wires everywhere
Groups	Rotated
Generated from a Verilog module

Note

These circuit layouts were copied from a digital design course given by prof. S. Zahno and recreated using this package

Click on the example image to jump to the code.

Usage

For more information, see the manual

To use this package, simply import circuiteria and call the circuit function:

#import "@preview/circuiteria:0.2.1"
#circuiteria.circuit({
  import circuiteria: *
  ...
})

Verilog modules

Blocks can be generated automatically from Verilog/SystemVerilog sources. AXI4, AXI4-Lite, AXI4-Stream and Vivado BRAM interface signals are grouped into single bus ports, and clock/reset signals are detected and placed together:

#circuiteria.circuit({
  import circuiteria: *
  verilog.block(read("my_module.v"), x: 0, y: 0)
})

The port ids are the signal names, or the bus prefixes for inferred buses (e.g. "my_module-port-s_axi").